Gabe Black 452f50f7cf x86: coreboot: Tell u-boot about PCI bus 0 when initializing ... U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>		2012-11-28 11:40:04 -08:00
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asm-offsets.c	x86: Initial commit for running as a coreboot payload	2011-12-19 13:26:15 +11:00
coreboot_car.S	x86: Initial commit for running as a coreboot payload	2011-12-19 13:26:15 +11:00
coreboot.c	x86: coreboot: Move non-board specific files to coreboot arch directory	2012-11-28 11:40:04 -08:00
ipchecksum.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00
Makefile	x86: coreboot: Move non-board specific files to coreboot arch directory	2012-11-28 11:40:04 -08:00
pci.c	x86: coreboot: Tell u-boot about PCI bus 0 when initializing	2012-11-28 11:40:04 -08:00
sdram.c	x86: Add infrastructure to extract an e820 table from the coreboot tables	2011-12-19 13:26:16 +11:00
sysinfo.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00
tables.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00