mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
18e48776a6
The rk_hdmi (shared functions for multiple HDMI mini-drivers) has been using devfdt_get_addr() to read the HDMI controller's IO base address. This will cause a failure with a live tree. This changes the driver to use dev_read_addr() which is safe both for flat trees and live trees. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <dw_hdmi.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include "rk_hdmi.h"
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#include "rk_vop.h" /* for rk_vop_probe_regulators */
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static const struct hdmi_phy_config rockchip_phy_config[] = {
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{
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.mpixelclock = 74250000,
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.sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
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}, {
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.mpixelclock = 148500000,
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.sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = 297000000,
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.sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = 584000000,
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.sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
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}, {
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.mpixelclock = ~0ul,
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.sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
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}
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};
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static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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.mpixelclock = 40000000,
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.cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
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}, {
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.mpixelclock = 65000000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 66000000,
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.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
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}, {
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.mpixelclock = 83500000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 146250000,
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.cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
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}, {
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.mpixelclock = 148500000,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}, {
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.mpixelclock = 272000000,
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.cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
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}, {
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.mpixelclock = 340000000,
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.cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
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}, {
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.mpixelclock = ~0ul,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}
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};
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int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
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}
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int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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hdmi->ioaddr = (ulong)dev_read_addr(dev);
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hdmi->mpll_cfg = rockchip_mpll_cfg;
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hdmi->phy_cfg = rockchip_phy_config;
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/* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
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hdmi->reg_io_width = 4;
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hdmi->phy_set = dw_hdmi_phy_cfg;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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return 0;
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}
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void rk_hdmi_probe_regulators(struct udevice *dev,
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const char * const *names, int cnt)
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{
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rk_vop_probe_regulators(dev, names, cnt);
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}
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int rk_hdmi_probe(struct udevice *dev)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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int ret;
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ret = dw_hdmi_phy_wait_for_hpd(hdmi);
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if (ret < 0) {
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debug("hdmi can not get hpd signal\n");
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return -1;
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}
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dw_hdmi_init(hdmi);
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dw_hdmi_phy_init(hdmi);
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return 0;
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}
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