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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
224 lines
5.0 KiB
C
224 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_H
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#define __DRV_CLK_MTK_H
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#include <linux/bitops.h>
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#define CLK_XTAL 0
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#define MHZ (1000 * 1000)
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#define HAVE_RST_BAR BIT(0)
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#define CLK_DOMAIN_SCPSYS BIT(0)
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#define CLK_MUX_SETCLR_UPD BIT(1)
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#define CLK_GATE_SETCLR BIT(0)
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#define CLK_GATE_SETCLR_INV BIT(1)
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#define CLK_GATE_NO_SETCLR BIT(2)
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#define CLK_GATE_NO_SETCLR_INV BIT(3)
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#define CLK_GATE_MASK GENMASK(3, 0)
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#define CLK_PARENT_APMIXED BIT(4)
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#define CLK_PARENT_TOPCKGEN BIT(5)
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#define CLK_PARENT_MASK GENMASK(5, 4)
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#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
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/* struct mtk_pll_data - hardware-specific PLLs data */
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struct mtk_pll_data {
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const int id;
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u32 reg;
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u32 pwr_reg;
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u32 en_mask;
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u32 pd_reg;
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int pd_shift;
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u32 flags;
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u32 rst_bar_mask;
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u64 fmax;
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u64 fmin;
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int pcwbits;
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int pcwibits;
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u32 pcw_reg;
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int pcw_shift;
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u32 pcw_chg_reg;
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};
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/**
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* struct mtk_fixed_clk - fixed clocks
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*
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* @id: index of clocks
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* @parent: index of parnet clocks
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* @rate: fixed rate
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*/
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struct mtk_fixed_clk {
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const int id;
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const int parent;
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unsigned long rate;
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};
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#define FIXED_CLK(_id, _parent, _rate) { \
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.id = _id, \
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.parent = _parent, \
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.rate = _rate, \
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}
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/**
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* struct mtk_fixed_factor - fixed multiplier and divider clocks
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*
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* @id: index of clocks
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* @parent: index of parnet clocks
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* @mult: multiplier
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* @div: divider
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* @flag: hardware-specific flags
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*/
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struct mtk_fixed_factor {
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const int id;
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const int parent;
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u32 mult;
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u32 div;
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u32 flags;
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};
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#define FACTOR(_id, _parent, _mult, _div, _flags) { \
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.id = _id, \
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.parent = _parent, \
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.mult = _mult, \
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.div = _div, \
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.flags = _flags, \
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}
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/**
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* struct mtk_composite - aggregate clock of mux, divider and gate clocks
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*
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* @id: index of clocks
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* @parent: index of parnet clocks
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* @mux_reg: hardware-specific mux register
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* @gate_reg: hardware-specific gate register
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* @mux_mask: mask to the mux bit field
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* @mux_shift: shift to the mux bit field
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* @gate_shift: shift to the gate bit field
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* @num_parents: number of parent clocks
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* @flags: hardware-specific flags
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*/
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struct mtk_composite {
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const int id;
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const int *parent;
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u32 mux_reg;
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u32 mux_set_reg;
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u32 mux_clr_reg;
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u32 upd_reg;
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u32 gate_reg;
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u32 mux_mask;
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signed char mux_shift;
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signed char upd_shift;
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signed char gate_shift;
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signed char num_parents;
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u16 flags;
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};
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#define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
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_flags) { \
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.id = _id, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_mask = BIT(_width) - 1, \
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.gate_reg = _reg, \
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.gate_shift = _gate, \
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.parent = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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}
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#define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
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MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
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#define MUX(_id, _parents, _reg, _shift, _width) { \
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.id = _id, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_mask = BIT(_width) - 1, \
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.gate_shift = -1, \
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.parent = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = 0, \
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}
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#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
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_mux_clr_ofs, _shift, _width, _gate, \
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_upd_ofs, _upd, _flags) { \
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.id = _id, \
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.mux_reg = _mux_ofs, \
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.mux_set_reg = _mux_set_ofs, \
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.mux_clr_reg = _mux_clr_ofs, \
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.upd_reg = _upd_ofs, \
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.upd_shift = _upd, \
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.mux_shift = _shift, \
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.mux_mask = BIT(_width) - 1, \
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.gate_reg = _mux_ofs, \
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.gate_shift = _gate, \
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.parent = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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}
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struct mtk_gate_regs {
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u32 sta_ofs;
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u32 clr_ofs;
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u32 set_ofs;
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};
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/**
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* struct mtk_gate - gate clocks
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*
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* @id: index of gate clocks
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* @parent: index of parnet clocks
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* @regs: hardware-specific mux register
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* @shift: shift to the gate bit field
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* @flags: hardware-specific flags
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*/
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struct mtk_gate {
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const int id;
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const int parent;
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const struct mtk_gate_regs *regs;
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int shift;
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u32 flags;
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};
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/* struct mtk_clk_tree - clock tree */
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struct mtk_clk_tree {
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unsigned long xtal_rate;
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unsigned long xtal2_rate;
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const int fdivs_offs;
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const int muxes_offs;
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const struct mtk_pll_data *plls;
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const struct mtk_fixed_clk *fclks;
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const struct mtk_fixed_factor *fdivs;
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const struct mtk_composite *muxes;
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};
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struct mtk_clk_priv {
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void __iomem *base;
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const struct mtk_clk_tree *tree;
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};
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struct mtk_cg_priv {
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void __iomem *base;
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const struct mtk_clk_tree *tree;
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const struct mtk_gate *gates;
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};
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extern const struct clk_ops mtk_clk_apmixedsys_ops;
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extern const struct clk_ops mtk_clk_topckgen_ops;
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extern const struct clk_ops mtk_clk_gate_ops;
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int mtk_common_clk_init(struct udevice *dev,
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const struct mtk_clk_tree *tree);
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int mtk_common_clk_gate_init(struct udevice *dev,
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const struct mtk_clk_tree *tree,
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const struct mtk_gate *gates);
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#endif /* __DRV_CLK_MTK_H */
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