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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Joe Hershberger](/assets/img/avatar_default.png)
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
538 lines
13 KiB
C
538 lines
13 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* Ethernet test
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*
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* The Serial Communication Controllers (SCC) listed in ctlr_list array below
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* are tested in the loopback ethernet mode.
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* The controllers are configured accordingly and several packets
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* are transmitted. The configurable test parameters are:
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* MIN_PACKET_LENGTH - minimum size of packet to transmit
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* MAX_PACKET_LENGTH - maximum size of packet to transmit
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* TEST_NUM - number of tests
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_ETHER
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#if defined(CONFIG_8xx)
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#include <commproc.h>
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#elif defined(CONFIG_MPC8260)
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#include <asm/cpm_8260.h>
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#else
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#error "Apparently a bad configuration, please fix."
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#endif
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#include <command.h>
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#include <net.h>
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#include <serial.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MIN_PACKET_LENGTH 64
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#define MAX_PACKET_LENGTH 256
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#define TEST_NUM 1
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#define CTLR_SCC 0
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extern void spi_init_f (void);
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extern void spi_init_r (void);
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/* The list of controllers to test */
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#if defined(CONFIG_MPC823)
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static int ctlr_list[][2] = { {CTLR_SCC, 1} };
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#else
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static int ctlr_list[][2] = { };
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#endif
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static struct {
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void (*init) (int index);
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void (*halt) (int index);
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int (*send) (int index, volatile void *packet, int length);
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int (*recv) (int index, void *packet, int length);
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} ctlr_proc[1];
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static char *ctlr_name[1] = { "SCC" };
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define TOUT_LOOP 100
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static char txbuf[DBUF_LENGTH];
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* SCC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
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cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
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} RTXBD;
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static RTXBD *rtx;
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/*
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* SCC callbacks
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*/
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static void scc_init (int scc_index)
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{
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uchar ea[6];
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static int proff[] = {
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PROFF_SCC1,
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PROFF_SCC2,
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PROFF_SCC3,
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PROFF_SCC4,
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};
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static unsigned int cpm_cr[] = {
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CPM_CR_CH_SCC1,
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CPM_CR_CH_SCC2,
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CPM_CR_CH_SCC3,
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CPM_CR_CH_SCC4,
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};
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int i;
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scc_enet_t *pram_ptr;
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
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rxIdx = 0;
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txIdx = 0;
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
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dpram_alloc_align (sizeof (RTXBD), 8));
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#else
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rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
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#endif
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#if 0
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#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
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/* Configure port A pins for Txd and Rxd.
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*/
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immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
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immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
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immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
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#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
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/* Configure port B pins for Txd and Rxd.
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*/
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immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
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immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
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immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
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#else
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#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
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#endif
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#if defined(PC_ENET_LBK)
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/* Configure port C pins to disable External Loopback
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*/
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immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
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immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
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immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
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immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
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#endif /* PC_ENET_LBK */
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/* Configure port C pins to enable CLSN and RENA.
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*/
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immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
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immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
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immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
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/* Configure port A for TCLK and RCLK.
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*/
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immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
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immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
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/*
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* Configure Serial Interface clock routing -- see section 16.7.5.3
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* First, clear all SCC bits to zero, then set the ones we want.
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*/
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immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
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immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
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#else
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/*
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* SCC2 receive clock is BRG2
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* SCC2 transmit clock is BRG3
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*/
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immr->im_cpm.cp_brgc2 = 0x0001000C;
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immr->im_cpm.cp_brgc3 = 0x0001000C;
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immr->im_cpm.cp_sicr &= ~0x00003F00;
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immr->im_cpm.cp_sicr |= 0x00000a00;
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#endif /* 0 */
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/*
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* Initialize SDCR -- see section 16.9.23.7
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* SDMA configuration register
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*/
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immr->im_siu_conf.sc_sdcr = 0x01;
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/*
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* Setup SCC Ethernet Parameter RAM
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*/
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pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
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pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
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pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
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pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
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pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
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/*
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* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings:
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* Empty, Wrap
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*/
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for (i = 0; i < PKTBUFSRX; i++) {
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rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx->rxbd[i].cbd_datlen = 0; /* Reset */
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rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
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}
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/*
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* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings:
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* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
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*/
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for (i = 0; i < TX_BUF_CNT; i++) {
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rtx->txbd[i].cbd_sc =
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(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
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rtx->txbd[i].cbd_datlen = 0; /* Reset */
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rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
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}
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rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/*
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* Enter Command: Initialize Rx Params for SCC
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*/
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do { /* Spin until ready to issue command */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* Issue command */
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immr->im_cpm.cp_cpcr =
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((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
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CPM_CR_FLG);
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do { /* Spin until command processed */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/*
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* Ethernet Specific Parameter RAM
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* see table 13-16, pg. 660,
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* pg. 681 (example with suggested settings)
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*/
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pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
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pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
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pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
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pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
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pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
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pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
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pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
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pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
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pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
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pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
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pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
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pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
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pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
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pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
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pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
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eth_getenv_enetaddr("ethaddr", ea);
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pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
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pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
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pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
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pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
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pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
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pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
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pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
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pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
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pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
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/*
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* Enter Command: Initialize Tx Params for SCC
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*/
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do { /* Spin until ready to issue command */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* Issue command */
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immr->im_cpm.cp_cpcr =
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((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
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CPM_CR_FLG);
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do { /* Spin until command processed */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/*
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* Mask all Events in SCCM - we use polling mode
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*/
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immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
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/*
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* Clear Events in SCCE -- Clear bits by writing 1's
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*/
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immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
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/*
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* Initialize GSMR High 32-Bits
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* Settings: Normal Mode
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*/
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immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
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/*
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* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
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* Settings:
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* TCI = Invert
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* TPL = 48 bits
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* TPP = Repeating 10's
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* LOOP = Loopback
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* MODE = Ethernet
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*/
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immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
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SCC_GSMRL_TPL_48 |
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SCC_GSMRL_TPP_10 |
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SCC_GSMRL_DIAG_LOOP |
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SCC_GSMRL_MODE_ENET);
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/*
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* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
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*/
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immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
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/*
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* Initialize the PSMR
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* Settings:
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* CRC = 32-Bit CCITT
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* NIB = Begin searching for SFD 22 bits after RENA
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* LPB = Loopback Enable (Needed when FDE is set)
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*/
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immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
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SCC_PSMR_NIB22 | SCC_PSMR_LPB;
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/*
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* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
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*/
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immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
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(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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}
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static void scc_halt (int scc_index)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
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}
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static int scc_send (int index, volatile void *packet, int length)
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{
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int i, j = 0;
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
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udelay (1); /* will also trigger Wd if needed */
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j++;
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}
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if (j >= TOUT_LOOP)
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printf ("TX not ready\n");
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rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
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rtx->txbd[txIdx].cbd_datlen = length;
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rtx->txbd[txIdx].cbd_sc |=
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(BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
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udelay (1); /* will also trigger Wd if needed */
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j++;
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}
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if (j >= TOUT_LOOP)
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printf ("TX timeout\n");
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i = (rtx->txbd[txIdx].
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cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
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return i;
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}
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static int scc_recv (int index, void *packet, int max_length)
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{
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int length = -1;
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if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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goto Done; /* nothing received */
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}
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if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
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length = rtx->rxbd[rxIdx].cbd_datlen - 4;
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memcpy (packet,
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(void *)(net_rx_packets[rxIdx]),
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length < max_length ? length : max_length);
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}
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/* Give the buffer back to the SCC. */
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rtx->rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
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(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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} else {
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rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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Done:
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return length;
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}
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/*
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* Test routines
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*/
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static void packet_fill (char *packet, int length)
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{
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char c = (char) length;
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int i;
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packet[0] = 0xFF;
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packet[1] = 0xFF;
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packet[2] = 0xFF;
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packet[3] = 0xFF;
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packet[4] = 0xFF;
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packet[5] = 0xFF;
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for (i = 6; i < length; i++) {
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packet[i] = c++;
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}
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}
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static int packet_check (char *packet, int length)
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{
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char c = (char) length;
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int i;
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for (i = 6; i < length; i++) {
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if (packet[i] != c++)
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return -1;
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|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int test_ctlr (int ctlr, int index)
|
|
{
|
|
int res = -1;
|
|
char packet_send[MAX_PACKET_LENGTH];
|
|
char packet_recv[MAX_PACKET_LENGTH];
|
|
int length;
|
|
int i;
|
|
int l;
|
|
|
|
ctlr_proc[ctlr].init (index);
|
|
|
|
for (i = 0; i < TEST_NUM; i++) {
|
|
for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
|
|
packet_fill (packet_send, l);
|
|
|
|
ctlr_proc[ctlr].send (index, packet_send, l);
|
|
|
|
length = ctlr_proc[ctlr].recv (index, packet_recv,
|
|
MAX_PACKET_LENGTH);
|
|
|
|
if (length != l || packet_check (packet_recv, length) < 0) {
|
|
goto Done;
|
|
}
|
|
}
|
|
}
|
|
|
|
res = 0;
|
|
|
|
Done:
|
|
|
|
ctlr_proc[ctlr].halt (index);
|
|
|
|
/*
|
|
* SCC2 Ethernet parameter RAM space overlaps
|
|
* the SPI parameter RAM space. So we need to restore
|
|
* the SPI configuration after SCC2 ethernet test.
|
|
*/
|
|
#if defined(CONFIG_SPI)
|
|
if (ctlr == CTLR_SCC && index == 1) {
|
|
spi_init_f ();
|
|
spi_init_r ();
|
|
}
|
|
#endif
|
|
|
|
if (res != 0) {
|
|
post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
|
|
index + 1);
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
int ether_post_test (int flags)
|
|
{
|
|
int res = 0;
|
|
int i;
|
|
|
|
ctlr_proc[CTLR_SCC].init = scc_init;
|
|
ctlr_proc[CTLR_SCC].halt = scc_halt;
|
|
ctlr_proc[CTLR_SCC].send = scc_send;
|
|
ctlr_proc[CTLR_SCC].recv = scc_recv;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
|
|
if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
|
|
res = -1;
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_8xx_CONS_NONE)
|
|
serial_reinit_all ();
|
|
#endif
|
|
return res;
|
|
}
|
|
|
|
#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
|