mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
![Walter Schweizer](/assets/img/avatar_default.png)
Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
177 lines
3.7 KiB
C
177 lines
3.7 KiB
C
/*
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* Copyright (C) 2009-2012
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* Wojciech Dubowik <wojciech.dubowik@neratec.com>
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* Luka Perkov <luka@openwrt.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include "ds109.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(DS109_OE_VAL_LOW,
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DS109_OE_VAL_HIGH,
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DS109_OE_LOW, DS109_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_SPI_SCn, /* SPI Flash */
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_GPIO,
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MPP5_GPO,
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MPP6_SYSRST_OUTn, /* Reset signal */
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MPP7_GPO,
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MPP8_TW_SDA, /* I2C */
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MPP9_TW_SCK, /* I2C */
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO,
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MPP13_UART1_TXD,
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MPP14_UART1_RXD,
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MPP15_GPIO,
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MPP16_GPIO,
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MPP17_GPIO,
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MPP18_GPO,
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MPP19_GPO,
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP22_GPIO, /* HDD2 FAIL LED */
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MPP23_GPIO, /* HDD1 FAIL LED */
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO, /* HDD2 */
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MPP32_GPIO, /* FAN A */
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MPP33_GPIO, /* FAN B */
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MPP34_GPIO, /* FAN C */
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MPP35_GPIO, /* FAN SENSE */
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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/* Synology reset uses UART */
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#include <ns16550.h>
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#define SOFTWARE_SHUTDOWN 0x31
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#define SOFTWARE_REBOOT 0x43
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#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
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void reset_misc(void)
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{
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int b_d;
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printf("Synology reset...");
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udelay(50000);
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b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
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CONFIG_SYS_NS16550_CLK, 9600);
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
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}
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/* Support old kernels */
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void setup_board_tags(struct tag **in_params)
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{
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unsigned int boardId;
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struct tag *params;
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struct tag_mv_uboot *t;
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int i;
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printf("Synology board tags...");
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params = *in_params;
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t = (struct tag_mv_uboot *)¶ms->u;
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t->uboot_version = VER_NUM;
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boardId = SYNO_DS109_ID;
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t->uboot_version |= boardId;
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t->tclk = CONFIG_SYS_TCLK;
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t->sysclk = CONFIG_SYS_TCLK*2;
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t->isusbhost = 1;
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for (i = 0; i < 4; i++) {
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memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
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t->mtu[i] = 0;
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}
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params->hdr.tag = ATAG_MV_UBOOT;
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params->hdr.size = tag_size(tag_mv_uboot);
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params = tag_next(params);
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*in_params = params;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
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printf("Error: 88E1116 could not read PHY dev address\n");
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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