mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-08 03:03:45 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
110 lines
2.1 KiB
ArmAsm
110 lines
2.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014, NVIDIA
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* Copyright (C) 2015, Siemens AG
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*
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* Authors:
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* Thierry Reding <treding@nvidia.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*/
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/psci.h>
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define TEGRA_SB_CSR_0 0x6000c200
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#define NS_RST_VEC_WR_DIS (1 << 1)
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#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100
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#define TEGRA_FLOW_CTRL_BASE 0x60007000
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#define FLOW_CTRL_CPU_CSR 0x08
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#define CSR_ENABLE (1 << 0)
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#define CSR_IMMEDIATE_WAKE (1 << 3)
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#define CSR_WAIT_WFI_SHIFT 8
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#define FLOW_CTRL_CPU1_CSR 0x18
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@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
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.macro get_csr_reg cpu, ofs, tmp
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cmp \cpu, #0 @ CPU0?
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lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3)
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moveq \ofs, #FLOW_CTRL_CPU_CSR
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addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8
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.endm
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ENTRY(psci_arch_init)
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mov r6, lr
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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@ lock reset vector for non-secure
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ldr r4, =TEGRA_SB_CSR_0
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ldr r5, [r4]
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orr r5, r5, #NS_RST_VEC_WR_DIS
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str r5, [r4]
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bl psci_get_cpu_id @ CPU ID => r0
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adr r5, _sys_clock_freq
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cmp r0, #0
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mrceq p15, 0, r7, c14, c0, 0 @ read CNTFRQ from CPU0
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streq r7, [r5]
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ldrne r7, [r5]
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mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3
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bx r6
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ENDPROC(psci_arch_init)
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_sys_clock_freq:
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.word 0
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ENTRY(psci_cpu_off)
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bl psci_cpu_off_common
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bl psci_get_cpu_id @ CPU ID => r0
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get_csr_reg r0, r2, r3
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ldr r6, =TEGRA_FLOW_CTRL_BASE
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mov r5, #(CSR_ENABLE)
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mov r4, #(1 << CSR_WAIT_WFI_SHIFT)
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add r5, r4, lsl r0
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str r5, [r6, r2]
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_loop: wfi
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b _loop
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ENDPROC(psci_cpu_off)
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ENTRY(psci_cpu_on)
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push {r4, r5, r6, lr}
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mov r4, r1
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mov r0, r1
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mov r1, r2
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bl psci_save_target_pc @ store target PC
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mov r1, r4
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ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
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ldr r5, =psci_cpu_entry
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str r5, [r6]
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get_csr_reg r1, r2, r3
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ldr r6, =TEGRA_FLOW_CTRL_BASE
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mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE)
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str r5, [r6, r2]
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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pop {r4, r5, r6, pc}
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ENDPROC(psci_cpu_on)
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.popsection
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