mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
302 lines
6.1 KiB
C
302 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012
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* Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <linux/errno.h>
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#include <mv88e6352.h>
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#define SMI_HDR ((0x8 | 0x1) << 12)
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#define SMI_BUSY_MASK (0x8000)
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#define SMIRD_OP (0x2 << 10)
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#define SMIWR_OP (0x1 << 10)
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#define SMI_MASK 0x1f
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#define PORT_SHIFT 5
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#define COMMAND_REG 0
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#define DATA_REG 1
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/* global registers */
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#define GLOBAL 0x1b
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#define GLOBAL_STATUS 0x00
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#define PPU_STATE 0x8000
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#define GLOBAL_CTRL 0x04
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#define SW_RESET 0x8000
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#define PPU_ENABLE 0x4000
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static int sw_wait_rdy(const char *devname, u8 phy_addr)
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{
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u16 command;
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u32 timeout = 100;
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int ret;
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/* wait till the SMI is not busy */
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do {
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/* read command register */
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ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
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if (ret < 0) {
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printf("%s: Error reading command register\n",
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__func__);
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return ret;
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}
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if (timeout-- == 0) {
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printf("Err..(%s) SMI busy timeout\n", __func__);
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return -EFAULT;
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}
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} while (command & SMI_BUSY_MASK);
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return 0;
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}
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static int sw_reg_read(const char *devname, u8 phy_addr, u8 port,
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u8 reg, u16 *data)
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{
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int ret;
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u16 command;
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ret = sw_wait_rdy(devname, phy_addr);
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if (ret)
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return ret;
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command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) |
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(reg & SMI_MASK);
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debug("%s: write to command: %#x\n", __func__, command);
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ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
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if (ret)
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return ret;
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ret = sw_wait_rdy(devname, phy_addr);
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if (ret)
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return ret;
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ret = miiphy_read(devname, phy_addr, DATA_REG, data);
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return ret;
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}
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static int sw_reg_write(const char *devname, u8 phy_addr, u8 port,
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u8 reg, u16 data)
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{
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int ret;
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u16 value;
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ret = sw_wait_rdy(devname, phy_addr);
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if (ret)
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return ret;
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debug("%s: write to data: %#x\n", __func__, data);
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ret = miiphy_write(devname, phy_addr, DATA_REG, data);
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if (ret)
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return ret;
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value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) |
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(reg & SMI_MASK);
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debug("%s: write to command: %#x\n", __func__, value);
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ret = miiphy_write(devname, phy_addr, COMMAND_REG, value);
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if (ret)
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return ret;
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ret = sw_wait_rdy(devname, phy_addr);
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if (ret)
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return ret;
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return 0;
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}
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static int ppu_enable(const char *devname, u8 phy_addr)
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{
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int i, ret = 0;
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u16 reg;
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ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
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if (ret) {
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printf("%s: Error reading global ctrl reg\n", __func__);
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return ret;
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}
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reg |= PPU_ENABLE;
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ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
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if (ret) {
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printf("%s: Error writing global ctrl reg\n", __func__);
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return ret;
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}
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for (i = 0; i < 1000; i++) {
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sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
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®);
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if ((reg & 0xc000) == 0xc000)
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return 0;
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udelay(1000);
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}
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return -ETIMEDOUT;
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}
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static int ppu_disable(const char *devname, u8 phy_addr)
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{
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int i, ret = 0;
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u16 reg;
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ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
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if (ret) {
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printf("%s: Error reading global ctrl reg\n", __func__);
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return ret;
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}
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reg &= ~PPU_ENABLE;
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ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
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if (ret) {
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printf("%s: Error writing global ctrl reg\n", __func__);
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return ret;
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}
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for (i = 0; i < 1000; i++) {
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sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
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®);
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if ((reg & 0xc000) != 0xc000)
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return 0;
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udelay(1000);
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}
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return -ETIMEDOUT;
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}
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int mv88e_sw_program(const char *devname, u8 phy_addr,
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struct mv88e_sw_reg *regs, int regs_nb)
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{
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int i, ret = 0;
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/* first we need to disable the PPU */
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ret = ppu_disable(devname, phy_addr);
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if (ret) {
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printf("%s: Error disabling PPU\n", __func__);
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return ret;
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}
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for (i = 0; i < regs_nb; i++) {
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ret = sw_reg_write(devname, phy_addr, regs[i].port,
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regs[i].reg, regs[i].value);
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if (ret) {
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printf("%s: Error configuring switch\n", __func__);
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ppu_enable(devname, phy_addr);
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return ret;
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}
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}
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/* re-enable the PPU */
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ret = ppu_enable(devname, phy_addr);
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if (ret) {
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printf("%s: Error enabling PPU\n", __func__);
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return ret;
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}
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return 0;
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}
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int mv88e_sw_reset(const char *devname, u8 phy_addr)
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{
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int i, ret = 0;
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u16 reg;
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ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
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if (ret) {
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printf("%s: Error reading global ctrl reg\n", __func__);
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return ret;
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}
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reg = SW_RESET | PPU_ENABLE | 0x0400;
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ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
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if (ret) {
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printf("%s: Error writing global ctrl reg\n", __func__);
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return ret;
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}
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for (i = 0; i < 1000; i++) {
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sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
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®);
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if ((reg & 0xc800) != 0xc800)
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return 0;
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udelay(1000);
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}
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return -ETIMEDOUT;
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}
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int do_mvsw_reg_read(const char *name, int argc, char * const argv[])
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{
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u16 value = 0, phyaddr, reg, port;
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int ret;
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phyaddr = simple_strtoul(argv[1], NULL, 10);
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port = simple_strtoul(argv[2], NULL, 10);
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reg = simple_strtoul(argv[3], NULL, 10);
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ret = sw_reg_read(name, phyaddr, port, reg, &value);
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printf("%#x\n", value);
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return ret;
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}
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int do_mvsw_reg_write(const char *name, int argc, char * const argv[])
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{
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u16 value = 0, phyaddr, reg, port;
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int ret;
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phyaddr = simple_strtoul(argv[1], NULL, 10);
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port = simple_strtoul(argv[2], NULL, 10);
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reg = simple_strtoul(argv[3], NULL, 10);
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value = simple_strtoul(argv[4], NULL, 16);
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ret = sw_reg_write(name, phyaddr, port, reg, value);
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return ret;
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}
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int do_mvsw_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int ret;
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const char *cmd, *ethname;
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if (argc < 2)
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return cmd_usage(cmdtp);
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cmd = argv[1];
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--argc;
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++argv;
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if (strcmp(cmd, "read") == 0) {
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if (argc < 5)
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return cmd_usage(cmdtp);
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ethname = argv[1];
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--argc;
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++argv;
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ret = do_mvsw_reg_read(ethname, argc, argv);
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} else if (strcmp(cmd, "write") == 0) {
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if (argc < 6)
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return cmd_usage(cmdtp);
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ethname = argv[1];
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--argc;
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++argv;
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ret = do_mvsw_reg_write(ethname, argc, argv);
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} else
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return cmd_usage(cmdtp);
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return ret;
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}
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U_BOOT_CMD(
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mvsw_reg, 7, 1, do_mvsw_reg,
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"marvell 88e6352 switch register access",
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"write ethname phyaddr port reg value\n"
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"mvsw_reg read ethname phyaddr port reg\n"
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);
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