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https://github.com/brain-hackers/u-boot-brain
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6901aab8e3
Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
20 lines
581 B
Makefile
20 lines
581 B
Makefile
#
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# Copyright (C) 2018 Amarula Solutions.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
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obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
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obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
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obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
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obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
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obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
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obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
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obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
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obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
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obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
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obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
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obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
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