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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
236 lines
5.7 KiB
C
236 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_ACPI_PMC
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <acpi/acpi_s3.h>
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#ifdef CONFIG_X86
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#include <asm/intel_pinctrl.h>
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#endif
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#include <asm/io.h>
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#include <power/acpi_pmc.h>
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struct tco_regs {
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u32 tco_rld;
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u32 tco_sts;
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u32 tco1_cnt;
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u32 tco_tmr;
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};
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enum {
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TCO_STS_TIMEOUT = 1 << 3,
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TCO_STS_SECOND_TO_STS = 1 << 17,
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TCO1_CNT_HLT = 1 << 11,
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};
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#ifdef CONFIG_X86
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static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum)
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{
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return upriv->gpe0_dwx_shift_base + regnum * 4;
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}
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int pmc_gpe_init(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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struct udevice *itss;
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u32 *dw;
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u32 gpio_cfg_mask;
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u32 gpio_cfg;
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int ret, i;
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u32 mask;
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if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC)
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return log_msg_ret("uclass", -EPROTONOSUPPORT);
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dw = upriv->gpe0_dw;
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mask = upriv->gpe0_dwx_mask;
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gpio_cfg_mask = 0;
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for (i = 0; i < upriv->gpe0_count; i++) {
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gpio_cfg_mask |= mask << gpe0_shift(upriv, i);
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if (dw[i] & ~mask)
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return log_msg_ret("Base GPE0 value", -EINVAL);
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}
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/*
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* Route the GPIOs to the GPE0 block. Determine that all values
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* are different and if they aren't, use the reset values.
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*/
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if (dw[0] == dw[1] || dw[1] == dw[2]) {
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log_info("PMC: Using default GPE route");
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gpio_cfg = readl(upriv->gpe_cfg);
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for (i = 0; i < upriv->gpe0_count; i++)
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dw[i] = gpio_cfg >> gpe0_shift(upriv, i);
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} else {
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gpio_cfg = 0;
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for (i = 0; i < upriv->gpe0_count; i++)
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gpio_cfg |= dw[i] << gpe0_shift(upriv, i);
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clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg);
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}
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/* Set the routes in the GPIO communities as well */
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ret = uclass_first_device_err(UCLASS_IRQ, &itss);
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if (ret)
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return log_msg_ret("Cannot find itss", ret);
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pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]);
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return 0;
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}
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#endif /* CONFIG_X86 */
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static void pmc_fill_pm_reg_info(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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int i;
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upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
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upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
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upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
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log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
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upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
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for (i = 0; i < GPE0_REG_MAX; i++) {
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upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
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upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
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log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
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upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
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}
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}
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int pmc_disable_tco_base(ulong tco_base)
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{
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struct tco_regs *regs = (struct tco_regs *)tco_base;
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debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT);
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setio_32(®s->tco1_cnt, TCO1_CNT_HLT);
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return 0;
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}
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int pmc_init(struct udevice *dev)
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{
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const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
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int ret;
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pmc_fill_pm_reg_info(dev);
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if (!ops->init)
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return -ENOSYS;
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ret = ops->init(dev);
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if (ret)
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return log_msg_ret("Failed to init pmc", ret);
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#ifdef DEBUG
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pmc_dump_info(dev);
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#endif
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return 0;
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}
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int pmc_prev_sleep_state(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
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int prev_sleep_state = ACPI_S0; /* Default to S0 */
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if (upriv->pm1_sts & WAK_STS) {
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switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) {
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case ACPI_S3:
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if (IS_ENABLED(HAVE_ACPI_RESUME))
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prev_sleep_state = ACPI_S3;
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break;
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case ACPI_S5:
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prev_sleep_state = ACPI_S5;
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break;
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default:
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break;
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}
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/* Clear SLP_TYP */
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outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT);
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}
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if (!ops->prev_sleep_state)
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return prev_sleep_state;
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return ops->prev_sleep_state(dev, prev_sleep_state);
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}
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int pmc_disable_tco(struct udevice *dev)
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{
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const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
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pmc_fill_pm_reg_info(dev);
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if (!ops->disable_tco)
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return -ENOSYS;
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return ops->disable_tco(dev);
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}
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int pmc_global_reset_set_enable(struct udevice *dev, bool enable)
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{
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const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
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if (!ops->global_reset_set_enable)
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return -ENOSYS;
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return ops->global_reset_set_enable(dev, enable);
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}
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void pmc_dump_info(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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int i;
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printf("Device: %s\n", dev->name);
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printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n",
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upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2,
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upriv->gpe_cfg);
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printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
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upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
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for (i = 0; i < GPE0_REG_MAX; i++) {
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printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
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upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
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}
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printf("prsts: %08x\n", upriv->prsts);
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printf("tco_sts: %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts);
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printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
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upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
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}
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int pmc_ofdata_to_uc_platdata(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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int ret;
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ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask);
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if (ret)
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return log_msg_ret("no gpe0-dwx-mask", ret);
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ret = dev_read_u32(dev, "gpe0-dwx-shift-base",
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&upriv->gpe0_dwx_shift_base);
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if (ret)
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return log_msg_ret("no gpe0-dwx-shift-base", ret);
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ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg);
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if (ret)
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return log_msg_ret("no gpe0-sts", ret);
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upriv->gpe0_sts_reg += upriv->acpi_base;
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ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg);
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if (ret)
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return log_msg_ret("no gpe0-en", ret);
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upriv->gpe0_en_reg += upriv->acpi_base;
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return 0;
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}
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UCLASS_DRIVER(acpi_pmc) = {
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.id = UCLASS_ACPI_PMC,
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.name = "power-mgr",
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.per_device_auto = sizeof(struct acpi_pmc_upriv),
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};
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