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![Simon Glass](/assets/img/avatar_default.png)
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
824 lines
19 KiB
C
824 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ethernet driver for TI K2HK EVM.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <console.h>
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#include <linux/delay.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <net.h>
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#include <phy.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <asm/ti-common/keystone_nav.h>
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#include <asm/ti-common/keystone_net.h>
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#include <asm/ti-common/keystone_serdes.h>
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#include <asm/arch/psc_defs.h>
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#include <linux/libfdt.h>
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#include "cpsw_mdio.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef KEYSTONE2_EMAC_GIG_ENABLE
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#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
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#else
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#define emac_gigabit_enable(x) /* no gigabit to enable */
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#endif
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#define RX_BUFF_NUMS 24
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#define RX_BUFF_LEN 1520
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#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
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#define SGMII_ANEG_TIMEOUT 4000
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static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
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enum link_type {
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LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
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LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
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LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
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LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
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LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
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LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
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LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
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LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
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LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
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LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
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};
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#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
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((mac)[2] << 16) | ((mac)[3] << 24))
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#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
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#ifdef CONFIG_KSNET_NETCP_V1_0
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#define EMAC_EMACSW_BASE_OFS 0x90800
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#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
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/* CPSW Switch slave registers */
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#define CPGMACSL_REG_SA_LO 0x10
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#define CPGMACSL_REG_SA_HI 0x14
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#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
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(x) * 0x30)
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#elif defined(CONFIG_KSNET_NETCP_V1_5)
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#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
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/* CPSW Switch slave registers */
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#define CPGMACSL_REG_SA_LO 0x308
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#define CPGMACSL_REG_SA_HI 0x30c
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#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
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(x) * 0x1000)
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#endif
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struct ks2_eth_priv {
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struct udevice *dev;
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struct phy_device *phydev;
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struct mii_dev *mdio_bus;
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int phy_addr;
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phy_interface_t phy_if;
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int phy_of_handle;
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int sgmii_link_type;
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void *mdio_base;
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struct rx_buff_desc net_rx_buffs;
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struct pktdma_cfg *netcp_pktdma;
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void *hd;
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int slave_port;
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enum link_type link_type;
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bool emac_open;
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bool has_mdio;
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};
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static void __attribute__((unused))
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keystone2_eth_gigabit_enable(struct udevice *dev)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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/*
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* Check if link detected is giga-bit
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* If Gigabit mode detected, enable gigbit in MAC
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*/
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if (priv->has_mdio) {
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if (priv->phydev->speed != 1000)
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return;
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}
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writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
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CPGMACSL_REG_CTL) |
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EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
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DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
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}
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#ifdef CONFIG_SOC_K2G
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int keystone_rgmii_config(struct phy_device *phy_dev)
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{
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unsigned int i, status;
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i = 0;
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do {
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if (i > SGMII_ANEG_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phy_dev->link = 0;
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return 0;
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}
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if (ctrlc()) {
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puts("user interrupt!\n");
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phy_dev->link = 0;
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return -EINTR;
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}
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if ((i++ % 500) == 0)
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printf(".");
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udelay(1000); /* 1 ms */
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status = readl(RGMII_STATUS_REG);
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} while (!(status & RGMII_REG_STATUS_LINK));
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puts(" done\n");
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return 0;
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}
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#else
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int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
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{
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unsigned int i, status, mask;
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unsigned int mr_adv_ability, control;
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switch (interface) {
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case SGMII_LINK_MAC_MAC_AUTONEG:
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mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
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SGMII_REG_MR_ADV_LINK |
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SGMII_REG_MR_ADV_FULL_DUPLEX |
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SGMII_REG_MR_ADV_GIG_MODE);
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control = (SGMII_REG_CONTROL_MASTER |
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SGMII_REG_CONTROL_AUTONEG);
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break;
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case SGMII_LINK_MAC_PHY:
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case SGMII_LINK_MAC_PHY_FORCED:
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mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
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control = SGMII_REG_CONTROL_AUTONEG;
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break;
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case SGMII_LINK_MAC_MAC_FORCED:
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mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
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SGMII_REG_MR_ADV_LINK |
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SGMII_REG_MR_ADV_FULL_DUPLEX |
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SGMII_REG_MR_ADV_GIG_MODE);
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control = SGMII_REG_CONTROL_MASTER;
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break;
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case SGMII_LINK_MAC_FIBER:
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mr_adv_ability = 0x20;
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control = SGMII_REG_CONTROL_AUTONEG;
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break;
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default:
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mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
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control = SGMII_REG_CONTROL_AUTONEG;
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}
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__raw_writel(0, SGMII_CTL_REG(port));
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/*
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* Wait for the SerDes pll to lock,
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* but don't trap if lock is never read
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*/
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for (i = 0; i < 1000; i++) {
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udelay(2000);
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status = __raw_readl(SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LOCK) != 0)
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break;
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}
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__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
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__raw_writel(control, SGMII_CTL_REG(port));
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mask = SGMII_REG_STATUS_LINK;
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if (control & SGMII_REG_CONTROL_AUTONEG)
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mask |= SGMII_REG_STATUS_AUTONEG;
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status = __raw_readl(SGMII_STATUS_REG(port));
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if ((status & mask) == mask)
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return 0;
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printf("\n%s Waiting for SGMII auto negotiation to complete",
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phy_dev->dev->name);
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while ((status & mask) != mask) {
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/*
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* Timeout reached ?
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*/
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if (i > SGMII_ANEG_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phy_dev->link = 0;
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return 0;
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}
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if (ctrlc()) {
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puts("user interrupt!\n");
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phy_dev->link = 0;
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return -EINTR;
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}
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if ((i++ % 500) == 0)
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printf(".");
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udelay(1000); /* 1 ms */
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status = __raw_readl(SGMII_STATUS_REG(port));
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}
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puts(" done\n");
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return 0;
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}
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#endif
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int mac_sl_reset(u32 port)
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{
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u32 i, v;
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if (port >= DEVICE_N_GMACSL_PORTS)
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return GMACSL_RET_INVALID_PORT;
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/* Set the soft reset bit */
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writel(CPGMAC_REG_RESET_VAL_RESET,
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DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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/* Wait for the bit to clear */
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for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
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v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
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CPGMAC_REG_RESET_VAL_RESET)
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return GMACSL_RET_OK;
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}
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/* Timeout on the reset */
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return GMACSL_RET_WARN_RESET_INCOMPLETE;
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}
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int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
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{
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u32 v, i;
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int ret = GMACSL_RET_OK;
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if (port >= DEVICE_N_GMACSL_PORTS)
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return GMACSL_RET_INVALID_PORT;
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if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
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cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
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ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
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}
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/* Must wait if the device is undergoing reset */
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for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
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v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
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CPGMAC_REG_RESET_VAL_RESET)
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break;
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}
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if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
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return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
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writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
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writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
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#ifndef CONFIG_SOC_K2HK
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/* Map RX packet flow priority to 0 */
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writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
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#endif
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return ret;
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}
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int ethss_config(u32 ctl, u32 max_pkt_size)
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{
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u32 i;
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/* Max length register */
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writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
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/* Control register */
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writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
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/* All statistics enabled by default */
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writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
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DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
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/* Reset and enable the ALE */
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writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
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CPSW_REG_VAL_ALE_CTL_BYPASS,
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DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
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/* All ports put into forward mode */
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for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
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writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
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DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
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return 0;
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}
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int ethss_start(void)
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{
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int i;
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struct mac_sl_cfg cfg;
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cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
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cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
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for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
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mac_sl_reset(i);
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mac_sl_config(i, &cfg);
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}
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return 0;
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}
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int ethss_stop(void)
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{
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int i;
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for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
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mac_sl_reset(i);
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return 0;
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}
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struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
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.clk = SERDES_CLOCK_156P25M,
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.rate = SERDES_RATE_5G,
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.rate_mode = SERDES_QUARTER_RATE,
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.intf = SERDES_PHY_SGMII,
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.loopback = 0,
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};
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#ifndef CONFIG_SOC_K2G
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static void keystone2_net_serdes_setup(void)
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{
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ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
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&ks2_serdes_sgmii_156p25mhz,
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CONFIG_KSNET_SERDES_LANES_PER_SGMII);
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#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
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ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
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&ks2_serdes_sgmii_156p25mhz,
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CONFIG_KSNET_SERDES_LANES_PER_SGMII);
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#endif
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/* wait till setup */
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udelay(5000);
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}
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#endif
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static int ks2_eth_start(struct udevice *dev)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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#ifdef CONFIG_SOC_K2G
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keystone_rgmii_config(priv->phydev);
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#else
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keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
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priv->sgmii_link_type);
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#endif
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udelay(10000);
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/* On chip switch configuration */
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ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
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qm_init();
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if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
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pr_err("ksnav_init failed\n");
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goto err_knav_init;
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}
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/*
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* Streaming switch configuration. If not present this
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* statement is defined to void in target.h.
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* If present this is usually defined to a series of register writes
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*/
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hw_config_streaming_switch();
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if (priv->has_mdio) {
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phy_startup(priv->phydev);
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if (priv->phydev->link == 0) {
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pr_err("phy startup failed\n");
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goto err_phy_start;
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}
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}
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emac_gigabit_enable(dev);
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ethss_start();
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priv->emac_open = true;
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return 0;
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err_phy_start:
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ksnav_close(priv->netcp_pktdma);
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err_knav_init:
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qm_close();
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return -EFAULT;
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}
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static int ks2_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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genphy_update_link(priv->phydev);
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if (priv->phydev->link == 0)
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return -1;
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if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
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length = EMAC_MIN_ETHERNET_PKT_SIZE;
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return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
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length, (priv->slave_port) << 16);
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}
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static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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int pkt_size;
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u32 *pkt = NULL;
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priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
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if (priv->hd == NULL)
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return -EAGAIN;
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*packetp = (uchar *)pkt;
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return pkt_size;
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}
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static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
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int length)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
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return 0;
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}
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static void ks2_eth_stop(struct udevice *dev)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
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if (!priv->emac_open)
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return;
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ethss_stop();
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ksnav_close(priv->netcp_pktdma);
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qm_close();
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phy_shutdown(priv->phydev);
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priv->emac_open = false;
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}
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int ks2_eth_read_rom_hwaddr(struct udevice *dev)
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{
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struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
u32 maca = 0;
|
|
u32 macb = 0;
|
|
|
|
/* Read the e-fuse mac address */
|
|
if (priv->slave_port == 1) {
|
|
maca = __raw_readl(MAC_ID_BASE_ADDR);
|
|
macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
|
|
}
|
|
|
|
pdata->enetaddr[0] = (macb >> 8) & 0xff;
|
|
pdata->enetaddr[1] = (macb >> 0) & 0xff;
|
|
pdata->enetaddr[2] = (maca >> 24) & 0xff;
|
|
pdata->enetaddr[3] = (maca >> 16) & 0xff;
|
|
pdata->enetaddr[4] = (maca >> 8) & 0xff;
|
|
pdata->enetaddr[5] = (maca >> 0) & 0xff;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ks2_eth_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
writel(mac_hi(pdata->enetaddr),
|
|
DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
|
|
CPGMACSL_REG_SA_HI);
|
|
writel(mac_lo(pdata->enetaddr),
|
|
DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
|
|
CPGMACSL_REG_SA_LO);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks2_eth_probe(struct udevice *dev)
|
|
{
|
|
struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
struct mii_dev *mdio_bus;
|
|
|
|
priv->dev = dev;
|
|
priv->emac_open = false;
|
|
|
|
/* These clock enables has to be moved to common location */
|
|
if (cpu_is_k2g())
|
|
writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
|
|
|
|
/* By default, select PA PLL clock as PA clock source */
|
|
#ifndef CONFIG_SOC_K2G
|
|
if (psc_enable_module(KS2_LPSC_PA))
|
|
return -EACCES;
|
|
#endif
|
|
if (psc_enable_module(KS2_LPSC_CPGMAC))
|
|
return -EACCES;
|
|
if (psc_enable_module(KS2_LPSC_CRYPTO))
|
|
return -EACCES;
|
|
|
|
if (cpu_is_k2e() || cpu_is_k2l())
|
|
pll_pa_clk_sel();
|
|
|
|
priv->net_rx_buffs.buff_ptr = rx_buffs;
|
|
priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
|
|
priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
|
|
|
|
if (priv->slave_port == 1) {
|
|
#ifndef CONFIG_SOC_K2G
|
|
keystone2_net_serdes_setup();
|
|
#endif
|
|
/*
|
|
* Register MDIO bus for slave 0 only, other slave have
|
|
* to re-use the same
|
|
*/
|
|
mdio_bus = cpsw_mdio_init("ethernet-mdio",
|
|
(u32)priv->mdio_base,
|
|
EMAC_MDIO_CLOCK_FREQ,
|
|
EMAC_MDIO_BUS_FREQ);
|
|
if (!mdio_bus) {
|
|
pr_err("MDIO alloc failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
priv->mdio_bus = mdio_bus;
|
|
} else {
|
|
/* Get the MDIO bus from slave 0 device */
|
|
struct ks2_eth_priv *parent_priv;
|
|
|
|
parent_priv = dev_get_priv(dev->parent);
|
|
priv->mdio_bus = parent_priv->mdio_bus;
|
|
priv->mdio_base = parent_priv->mdio_base;
|
|
}
|
|
|
|
priv->netcp_pktdma = &netcp_pktdma;
|
|
|
|
if (priv->has_mdio) {
|
|
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
|
|
dev, priv->phy_if);
|
|
#ifdef CONFIG_DM_ETH
|
|
if (priv->phy_of_handle)
|
|
priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
|
|
#endif
|
|
phy_config(priv->phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ks2_eth_remove(struct udevice *dev)
|
|
{
|
|
struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
cpsw_mdio_free(priv->mdio_bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops ks2_eth_ops = {
|
|
.start = ks2_eth_start,
|
|
.send = ks2_eth_send,
|
|
.recv = ks2_eth_recv,
|
|
.free_pkt = ks2_eth_free_pkt,
|
|
.stop = ks2_eth_stop,
|
|
.read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
|
|
.write_hwaddr = ks2_eth_write_hwaddr,
|
|
};
|
|
|
|
static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
|
|
{
|
|
const void *fdt = gd->fdt_blob;
|
|
struct udevice *sl_dev;
|
|
int interfaces;
|
|
int sec_slave;
|
|
int slave;
|
|
int ret;
|
|
char *slave_name;
|
|
|
|
interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
|
|
fdt_for_each_subnode(slave, fdt, interfaces) {
|
|
int slave_no;
|
|
|
|
slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
|
|
if (slave_no == -ENOENT)
|
|
continue;
|
|
|
|
if (slave_no == 0) {
|
|
/* This is the current eth device */
|
|
*gbe_0 = slave;
|
|
} else {
|
|
/* Slave devices to be registered */
|
|
slave_name = malloc(20);
|
|
snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
|
|
ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
|
|
slave_name, offset_to_ofnode(slave),
|
|
&sl_dev);
|
|
if (ret) {
|
|
pr_err("ks2_net - not able to bind slave interfaces\n");
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
|
|
fdt_for_each_subnode(slave, fdt, sec_slave) {
|
|
int slave_no;
|
|
|
|
slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
|
|
if (slave_no == -ENOENT)
|
|
continue;
|
|
|
|
/* Slave devices to be registered */
|
|
slave_name = malloc(20);
|
|
snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
|
|
ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
|
|
offset_to_ofnode(slave), &sl_dev);
|
|
if (ret) {
|
|
pr_err("ks2_net - not able to bind slave interfaces\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks2_eth_parse_slave_interface(int netcp, int slave,
|
|
struct ks2_eth_priv *priv,
|
|
struct eth_pdata *pdata)
|
|
{
|
|
const void *fdt = gd->fdt_blob;
|
|
int mdio;
|
|
int phy;
|
|
int dma_count;
|
|
u32 dma_channel[8];
|
|
const char *phy_mode;
|
|
|
|
priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
|
|
priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
|
|
|
|
/* U-Boot slave port number starts with 1 instead of 0 */
|
|
priv->slave_port += 1;
|
|
|
|
dma_count = fdtdec_get_int_array_count(fdt, netcp,
|
|
"ti,navigator-dmas",
|
|
dma_channel, 8);
|
|
|
|
if (dma_count > (2 * priv->slave_port)) {
|
|
int dma_idx;
|
|
|
|
dma_idx = priv->slave_port * 2 - 1;
|
|
priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
|
|
}
|
|
|
|
priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
|
|
|
|
phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
|
|
|
|
if (phy >= 0) {
|
|
priv->phy_of_handle = phy;
|
|
priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
|
|
|
|
mdio = fdt_parent_offset(fdt, phy);
|
|
if (mdio < 0) {
|
|
pr_err("mdio dt not found\n");
|
|
return -ENODEV;
|
|
}
|
|
priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
|
|
}
|
|
|
|
if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
|
|
priv->phy_if = PHY_INTERFACE_MODE_SGMII;
|
|
pdata->phy_interface = priv->phy_if;
|
|
priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
|
|
priv->has_mdio = true;
|
|
} else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
|
|
phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
|
|
if (phy_mode) {
|
|
priv->phy_if = phy_get_interface_by_name(phy_mode);
|
|
if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
|
|
priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
|
|
priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
|
|
priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
|
|
pr_err("invalid phy-mode\n");
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
priv->phy_if = PHY_INTERFACE_MODE_RGMII;
|
|
}
|
|
pdata->phy_interface = priv->phy_if;
|
|
priv->has_mdio = true;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const void *fdt = gd->fdt_blob;
|
|
int slave = dev_of_offset(dev);
|
|
int interfaces;
|
|
int gbe;
|
|
int netcp_devices;
|
|
int netcp;
|
|
|
|
interfaces = fdt_parent_offset(fdt, slave);
|
|
gbe = fdt_parent_offset(fdt, interfaces);
|
|
netcp_devices = fdt_parent_offset(fdt, gbe);
|
|
netcp = fdt_parent_offset(fdt, netcp_devices);
|
|
|
|
ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
|
|
|
|
pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct ks2_eth_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const void *fdt = gd->fdt_blob;
|
|
int gbe_0 = -ENODEV;
|
|
int netcp_devices;
|
|
int gbe;
|
|
|
|
netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
|
|
"netcp-devices");
|
|
gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
|
|
|
|
ks2_eth_bind_slaves(dev, gbe, &gbe_0);
|
|
|
|
ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id ks2_eth_ids[] = {
|
|
{ .compatible = "ti,netcp-1.0" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_ks2_slave) = {
|
|
.name = "eth_ks2_sl",
|
|
.id = UCLASS_ETH,
|
|
.ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
|
|
.probe = ks2_eth_probe,
|
|
.remove = ks2_eth_remove,
|
|
.ops = &ks2_eth_ops,
|
|
.priv_auto = sizeof(struct ks2_eth_priv),
|
|
.platdata_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_ks2) = {
|
|
.name = "eth_ks2",
|
|
.id = UCLASS_ETH,
|
|
.of_match = ks2_eth_ids,
|
|
.ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
|
|
.probe = ks2_eth_probe,
|
|
.remove = ks2_eth_remove,
|
|
.ops = &ks2_eth_ops,
|
|
.priv_auto = sizeof(struct ks2_eth_priv),
|
|
.platdata_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|