663 lines
17 KiB
C
663 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/util.h>
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#include <dt-bindings/clock/agilex-clock.h>
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#include <linux/bitops.h>
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#include <asm/arch/clock_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct socfpga_clk_platdata {
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void __iomem *regs;
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};
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
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cm_wait_for_fsm();
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}
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static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
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cm_wait_for_fsm();
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}
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#define MEMBUS_MAINPLL 0
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#define MEMBUS_PERPLL 1
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#define MEMBUS_TIMEOUT 1000
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#define MEMBUS_CLKSLICE_REG 0x27
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#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3
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#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6
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#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03
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#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07
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static const struct {
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u32 reg;
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u32 val;
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u32 mask;
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} membus_pll[] = {
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{
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MEMBUS_CLKSLICE_REG,
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/*
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* BIT[7:7]
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* Enable source synchronous mode
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*/
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BIT(7),
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BIT(7)
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},
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{
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MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
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/*
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* BIT[0:0]
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* Sets synthcalfosc_init_centerfreq=1 to limit overshoot
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* frequency during lock
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*/
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BIT(0),
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BIT(0)
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},
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{
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MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG,
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/*
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* BIT[0:0]
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* Sets synthppm_watchdogtmr_vf0=1 to give the pll more time
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* to settle before lock is asserted.
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*/
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BIT(0),
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BIT(0)
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},
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{
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MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG,
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/*
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* BIT[6:0]
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* Centering duty cycle for clkslice0 output
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*/
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0x4a,
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GENMASK(6, 0)
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},
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{
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MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG,
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/*
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* BIT[6:0]
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* Centering duty cycle for clkslice1 output
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*/
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0x4a,
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GENMASK(6, 0)
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},
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};
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static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
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int timeout)
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{
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int cnt = 0;
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u32 req_status;
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if (pll == MEMBUS_MAINPLL)
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req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
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else
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req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
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while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
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if (pll == MEMBUS_MAINPLL)
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req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
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else
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req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
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cnt++;
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}
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if (cnt >= timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
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u32 addr_offset, u32 wdat, int timeout)
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{
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u32 addr;
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u32 val;
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addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
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val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
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(wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
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if (pll == MEMBUS_MAINPLL)
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
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else
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
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debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
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return membus_wait_for_req(plat, pll, timeout);
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}
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static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
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u32 addr_offset, u32 *rdata, int timeout)
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{
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u32 addr;
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u32 val;
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addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
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val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
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if (pll == MEMBUS_MAINPLL)
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
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else
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
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*rdata = 0;
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if (membus_wait_for_req(plat, pll, timeout))
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return -ETIMEDOUT;
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if (pll == MEMBUS_MAINPLL)
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*rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
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else
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*rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
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debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
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return 0;
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}
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static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
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{
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int i;
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u32 rdata;
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for (i = 0; i < ARRAY_SIZE(membus_pll); i++) {
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membus_read_pll(plat, pll, membus_pll[i].reg,
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&rdata, MEMBUS_TIMEOUT);
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membus_write_pll(plat, pll, membus_pll[i].reg,
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((rdata & ~membus_pll[i].mask) | membus_pll[i].val),
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MEMBUS_TIMEOUT);
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}
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}
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static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
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{
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u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
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mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
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arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
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drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
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refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
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mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
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if (!mscnt)
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mscnt = 1;
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hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
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CLKMGR_VCOCALIB_HSCNT_CONST;
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
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((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
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CLKMGR_VCOCALIB_MSCNT_MASK);
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/* Dump all the pll calibration settings for debug purposes */
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debug("mdiv : %d\n", mdiv);
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debug("arefclkdiv : %d\n", arefclkdiv);
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debug("drefclkdiv : %d\n", drefclkdiv);
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debug("refclkdiv : %d\n", refclkdiv);
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debug("mscnt : %d\n", mscnt);
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debug("hscnt : %d\n", hscnt);
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debug("vcocalib : 0x%08x\n", vcocalib);
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return vcocalib;
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*/
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static void clk_basic_init(struct udevice *dev,
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const struct cm_config * const cfg)
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{
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struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
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u32 vcocalib;
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if (!cfg)
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return;
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#ifdef CONFIG_SPL_BUILD
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/* Always force clock manager into boot mode before any configuration */
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clk_write_ctrl(plat,
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CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
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#else
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/* Skip clock configuration in SSBL if it's not in boot mode */
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if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
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return;
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#endif
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/* Put both PLLs in bypass */
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clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
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clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
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/* Put both PLLs in Reset and Power Down */
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CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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/* setup main PLL dividers where calculate the vcocalib value */
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vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
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CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
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CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
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CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
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CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
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CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
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/* setup peripheral PLL dividers where calculate the vcocalib value */
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vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
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CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
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CLKMGR_PERPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
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CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
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CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
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CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
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CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
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/* Take both PLL out of reset and power up */
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CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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/* Membus programming for mainpll */
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membus_pll_configs(plat, MEMBUS_MAINPLL);
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/* Membus programming for peripll */
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membus_pll_configs(plat, MEMBUS_PERPLL);
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cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
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/* Configure ping pong counters in altera group */
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CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
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CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
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CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
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CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
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CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
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CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_PERPLL_PLLGLOB);
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/* Take all PLLs out of bypass */
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clk_write_bypass_mainpll(plat, 0);
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clk_write_bypass_perpll(plat, 0);
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/* Clear the loss of lock bits (write 1 to clear) */
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CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
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CLKMGR_INTER_PERPLLLOST_MASK |
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CLKMGR_INTER_MAINPLLLOST_MASK);
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/* Take all ping pong counters out of reset */
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CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
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CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
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/* Out of boot mode */
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clk_write_ctrl(plat,
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CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
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}
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static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
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u32 pllglob_reg, u32 pllm_reg)
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{
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u64 fref, arefdiv, mdiv, reg, vco;
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reg = CM_REG_READL(plat, pllglob_reg);
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fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
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CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
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switch (fref) {
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case CLKMGR_VCO_PSRC_EOSC1:
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fref = cm_get_osc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_INTOSC:
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fref = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_F2S:
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fref = cm_get_fpga_clk_hz();
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break;
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}
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arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
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mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
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vco = fref / arefdiv;
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vco = vco * mdiv;
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return vco;
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}
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static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
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{
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return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLM);
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}
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static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
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{
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return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLM);
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}
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static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
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{
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u32 clksrc = CM_REG_READL(plat, reg);
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return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
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}
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static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
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u32 main_reg, u32 per_reg)
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{
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u64 clock;
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u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
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switch (clklsrc) {
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case CLKMGR_CLKSRC_MAIN:
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clock = clk_get_main_vco_clk_hz(plat);
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clock /= (CM_REG_READL(plat, main_reg) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_PER:
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clock = clk_get_per_vco_clk_hz(plat);
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clock /= (CM_REG_READL(plat, per_reg) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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default:
|
|
return 0;
|
|
}
|
|
|
|
return clock;
|
|
}
|
|
|
|
static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
|
|
CLKMGR_MAINPLL_PLLC0,
|
|
CLKMGR_PERPLL_PLLC0);
|
|
|
|
clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
|
|
return clock;
|
|
}
|
|
|
|
static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
|
|
CLKMGR_MAINPLL_PLLC1,
|
|
CLKMGR_PERPLL_PLLC1);
|
|
}
|
|
|
|
static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
u64 clock = clk_get_l3_main_clk_hz(plat);
|
|
|
|
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
|
CLKMGR_NOCDIV_L4MAIN_OFFSET) &
|
|
CLKMGR_NOCDIV_DIVIDER_MASK);
|
|
|
|
return clock;
|
|
}
|
|
|
|
static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
|
|
CLKMGR_MAINPLL_PLLC3,
|
|
CLKMGR_PERPLL_PLLC3);
|
|
|
|
clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
|
|
return clock / 4;
|
|
}
|
|
|
|
static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
u64 clock = clk_get_l3_main_clk_hz(plat);
|
|
|
|
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
|
CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
|
|
CLKMGR_NOCDIV_DIVIDER_MASK);
|
|
|
|
return clock;
|
|
}
|
|
|
|
static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
u64 clock = clk_get_l3_main_clk_hz(plat);
|
|
|
|
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
|
CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
|
|
CLKMGR_NOCDIV_DIVIDER_MASK);
|
|
|
|
return clock;
|
|
}
|
|
|
|
static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
|
|
{
|
|
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
|
|
return clk_get_l3_main_clk_hz(plat) / 2;
|
|
|
|
return clk_get_l3_main_clk_hz(plat) / 4;
|
|
}
|
|
|
|
static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
|
|
{
|
|
bool emacsel_a;
|
|
u32 ctl;
|
|
u32 ctr_reg;
|
|
u32 clock;
|
|
u32 div;
|
|
u32 reg;
|
|
|
|
/* Get EMAC clock source */
|
|
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
|
|
if (emac_id == AGILEX_EMAC0_CLK)
|
|
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
|
|
CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
|
|
else if (emac_id == AGILEX_EMAC1_CLK)
|
|
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
|
|
CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
|
|
else if (emac_id == AGILEX_EMAC2_CLK)
|
|
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
|
|
CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
|
|
else
|
|
return 0;
|
|
|
|
if (ctl) {
|
|
/* EMAC B source */
|
|
emacsel_a = false;
|
|
ctr_reg = CLKMGR_ALTR_EMACBCTR;
|
|
} else {
|
|
/* EMAC A source */
|
|
emacsel_a = true;
|
|
ctr_reg = CLKMGR_ALTR_EMACACTR;
|
|
}
|
|
|
|
reg = CM_REG_READL(plat, ctr_reg);
|
|
clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
|
|
>> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
|
|
div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
|
|
>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
|
|
|
|
switch (clock) {
|
|
case CLKMGR_CLKSRC_MAIN:
|
|
clock = clk_get_main_vco_clk_hz(plat);
|
|
if (emacsel_a) {
|
|
clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
} else {
|
|
clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
}
|
|
break;
|
|
|
|
case CLKMGR_CLKSRC_PER:
|
|
clock = clk_get_per_vco_clk_hz(plat);
|
|
if (emacsel_a) {
|
|
clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
} else {
|
|
clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
|
|
CLKMGR_CLKCNT_MSK);
|
|
}
|
|
break;
|
|
|
|
case CLKMGR_CLKSRC_OSC1:
|
|
clock = cm_get_osc_clk_hz();
|
|
break;
|
|
|
|
case CLKMGR_CLKSRC_INTOSC:
|
|
clock = cm_get_intosc_clk_hz();
|
|
break;
|
|
|
|
case CLKMGR_CLKSRC_FPGA:
|
|
clock = cm_get_fpga_clk_hz();
|
|
break;
|
|
}
|
|
|
|
clock /= 1 + div;
|
|
|
|
return clock;
|
|
}
|
|
|
|
static ulong socfpga_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case AGILEX_MPU_CLK:
|
|
return clk_get_mpu_clk_hz(plat);
|
|
case AGILEX_L4_MAIN_CLK:
|
|
return clk_get_l4_main_clk_hz(plat);
|
|
case AGILEX_L4_SYS_FREE_CLK:
|
|
return clk_get_l4_sys_free_clk_hz(plat);
|
|
case AGILEX_L4_MP_CLK:
|
|
return clk_get_l4_mp_clk_hz(plat);
|
|
case AGILEX_L4_SP_CLK:
|
|
return clk_get_l4_sp_clk_hz(plat);
|
|
case AGILEX_SDMMC_CLK:
|
|
return clk_get_sdmmc_clk_hz(plat);
|
|
case AGILEX_EMAC0_CLK:
|
|
case AGILEX_EMAC1_CLK:
|
|
case AGILEX_EMAC2_CLK:
|
|
return clk_get_emac_clk_hz(plat, clk->id);
|
|
case AGILEX_USB_CLK:
|
|
case AGILEX_NAND_X_CLK:
|
|
return clk_get_l4_mp_clk_hz(plat);
|
|
case AGILEX_NAND_CLK:
|
|
return clk_get_l4_mp_clk_hz(plat) / 4;
|
|
default:
|
|
return -ENXIO;
|
|
}
|
|
}
|
|
|
|
static int socfpga_clk_enable(struct clk *clk)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int socfpga_clk_probe(struct udevice *dev)
|
|
{
|
|
const struct cm_config *cm_default_cfg = cm_get_default_config();
|
|
|
|
clk_basic_init(dev, cm_default_cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
|
|
fdt_addr_t addr;
|
|
|
|
addr = dev_read_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
plat->regs = (void __iomem *)addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops socfpga_clk_ops = {
|
|
.enable = socfpga_clk_enable,
|
|
.get_rate = socfpga_clk_get_rate,
|
|
};
|
|
|
|
static const struct udevice_id socfpga_clk_match[] = {
|
|
{ .compatible = "intel,agilex-clkmgr" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(socfpga_agilex_clk) = {
|
|
.name = "clk-agilex",
|
|
.id = UCLASS_CLK,
|
|
.of_match = socfpga_clk_match,
|
|
.ops = &socfpga_clk_ops,
|
|
.probe = socfpga_clk_probe,
|
|
.ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
|
|
.platdata_auto = sizeof(struct socfpga_clk_platdata),
|
|
};
|