229 lines
6.1 KiB
C
229 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot pmclib.c, pmc.c and pmutil.c
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*/
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#define LOG_CATEGORY UCLASS_ACPI_PMC
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#include <common.h>
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#include <dt-structs.h>
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#include <dm.h>
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#include <log.h>
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#include <spl.h>
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#include <acpi/acpi_s3.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <linux/bitops.h>
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#include <power/acpi_pmc.h>
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#define GPIO_GPE_CFG 0x1050
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PRSTS 0x1000
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#define GEN_PMCON1 0x1020
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#define COLD_BOOT_STS BIT(27)
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#define COLD_RESET_STS BIT(26)
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#define WARM_RESET_STS BIT(25)
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#define GLOBAL_RESET_STS BIT(24)
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#define SRS BIT(20)
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#define MS4V BIT(18)
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#define RPS BIT(2)
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#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
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WARM_RESET_STS | GLOBAL_RESET_STS | \
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SRS | MS4V)
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#define GEN_PMCON2 0x1024
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#define GEN_PMCON3 0x1028
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/* Offset of TCO registers from ACPI base I/O address */
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#define TCO_REG_OFFSET 0x60
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#define TCO1_STS 0x64
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#define DMISCI_STS BIT(9)
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#define BOOT_STS BIT(18)
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#define TCO2_STS 0x66
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#define TCO1_CNT 0x68
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#define TCO_LOCK BIT(12)
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#define TCO2_CNT 0x6a
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enum {
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ETR = 0x1048,
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CF9_LOCK = 1UL << 31,
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CF9_GLB_RST = 1 << 20,
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};
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struct apl_pmc_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_intel_apl_pmc dtplat;
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#endif
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pci_dev_t bdf;
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};
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static int apl_pmc_fill_power_state(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
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upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
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upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
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upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
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upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
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upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
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return 0;
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}
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static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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/* WAK_STS bit will not be set when waking from G3 state */
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if (!(upriv->pm1_sts & WAK_STS) &&
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(upriv->gen_pmcon1 & COLD_BOOT_STS))
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prev_sleep_state = ACPI_S5;
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return prev_sleep_state;
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}
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static int apl_disable_tco(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
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return 0;
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}
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static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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if (enable)
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setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
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else
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clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
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return 0;
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}
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int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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struct apl_pmc_platdata *plat = dev_get_platdata(dev);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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u32 base[6];
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int size;
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int ret;
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ret = dev_read_u32_array(dev, "early-regs", base,
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ARRAY_SIZE(base));
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if (ret)
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return log_msg_ret("Missing/short early-regs", ret);
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if (spl_phase() == PHASE_TPL) {
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upriv->pmc_bar0 = (void *)base[0];
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upriv->pmc_bar2 = (void *)base[2];
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/* Since PCI is not enabled, we must get the BDF manually */
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plat->bdf = pci_get_devfn(dev);
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if (plat->bdf < 0)
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return log_msg_ret("Cannot get PMC PCI address",
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plat->bdf);
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}
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upriv->acpi_base = base[4];
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/* Get the dwX values for pmc gpe settings */
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size = dev_read_size(dev, "gpe0-dw");
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if (size < 0)
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return log_msg_ret("Cannot read gpe0-dm", size);
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upriv->gpe0_count = size / sizeof(u32);
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ret = dev_read_u32_array(dev, "gpe0-dw", upriv->gpe0_dw,
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upriv->gpe0_count);
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if (ret)
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return log_msg_ret("Bad gpe0-dw", ret);
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return pmc_ofdata_to_uc_platdata(dev);
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#else
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struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
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plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
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upriv->pmc_bar0 = (void *)dtplat->early_regs[0];
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upriv->pmc_bar2 = (void *)dtplat->early_regs[2];
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upriv->acpi_base = dtplat->early_regs[4];
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upriv->gpe0_dwx_mask = dtplat->gpe0_dwx_mask;
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upriv->gpe0_dwx_shift_base = dtplat->gpe0_dwx_shift_base;
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upriv->gpe0_sts_reg = dtplat->gpe0_sts;
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upriv->gpe0_sts_reg += upriv->acpi_base;
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upriv->gpe0_en_reg = dtplat->gpe0_en;
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upriv->gpe0_en_reg += upriv->acpi_base;
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upriv->gpe0_count = min((int)ARRAY_SIZE(dtplat->gpe0_dw), GPE0_REG_MAX);
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memcpy(upriv->gpe0_dw, dtplat->gpe0_dw, sizeof(dtplat->gpe0_dw));
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#endif
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upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
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return 0;
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}
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static int enable_pmcbar(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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struct apl_pmc_platdata *priv = dev_get_platdata(dev);
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pci_dev_t pmc = priv->bdf;
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/*
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* Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit
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* BARs.
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*/
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pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0,
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PCI_SIZE_32);
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pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
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pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2,
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PCI_SIZE_32);
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pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32);
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pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base,
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PCI_SIZE_16);
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pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
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PCI_SIZE_16);
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return 0;
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}
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static int apl_pmc_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL) {
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return enable_pmcbar(dev);
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} else {
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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upriv->pmc_bar0 = (void *)dm_pci_read_bar32(dev, 0);
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upriv->pmc_bar2 = (void *)dm_pci_read_bar32(dev, 2);
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}
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return 0;
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}
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static struct acpi_pmc_ops apl_pmc_ops = {
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.init = apl_pmc_fill_power_state,
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.prev_sleep_state = apl_prev_sleep_state,
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.disable_tco = apl_disable_tco,
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.global_reset_set_enable = apl_global_reset_set_enable,
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};
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static const struct udevice_id apl_pmc_ids[] = {
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{ .compatible = "intel,apl-pmc" },
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{ }
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};
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U_BOOT_DRIVER(intel_apl_pmc) = {
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.name = "intel_apl_pmc",
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.id = UCLASS_ACPI_PMC,
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.of_match = apl_pmc_ids,
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.ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata,
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.probe = apl_pmc_probe,
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.ops = &apl_pmc_ops,
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.platdata_auto = sizeof(struct apl_pmc_platdata),
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};
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