mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
![Bin Meng](/assets/img/avatar_default.png)
Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
46 lines
1.2 KiB
Plaintext
46 lines
1.2 KiB
Plaintext
#
|
|
# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
config INTEL_QUEENSBAY
|
|
bool
|
|
select HAVE_FSP
|
|
select HAVE_CMC
|
|
|
|
if INTEL_QUEENSBAY
|
|
|
|
config HAVE_CMC
|
|
bool "Add a Chipset Micro Code state machine binary"
|
|
help
|
|
Select this option to add a Chipset Micro Code state machine binary
|
|
to the resulting U-Boot image. It is a 64K data block of machine
|
|
specific code which must be put in the flash for the processor to
|
|
access when powered up before system BIOS is executed.
|
|
|
|
config CMC_FILE
|
|
string "Chipset Micro Code state machine filename"
|
|
depends on HAVE_CMC
|
|
default "cmc.bin"
|
|
help
|
|
The filename of the file to use as Chipset Micro Code state machine
|
|
binary in the board directory.
|
|
|
|
config CMC_ADDR
|
|
hex "Chipset Micro Code state machine binary location"
|
|
depends on HAVE_CMC
|
|
default 0xfffb0000
|
|
help
|
|
The location of the CMC binary is determined by a strap. It must be
|
|
put in flash at a location matching the strap-determined base address.
|
|
|
|
The default base address of 0xfffb0000 indicates that the binary must
|
|
be located at offset 0xb0000 from the beginning of a 1MB flash device.
|
|
|
|
config CPU_ADDR_BITS
|
|
int
|
|
default 32
|
|
|
|
endif
|