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40f8dec54d
u-boot-brain/arch/arm/cpu/armv8
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York Sun 40f8dec54d armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25 08:36:19 -07:00
..
fsl-lsch3 armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
cache_v8.c ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
cache.S ARMv8: fix bug for flush data cache by set/way 2014-04-07 22:27:22 +02:00
config.mk arm: Switch to -mno-unaligned-access when supported by the compiler 2014-02-26 21:19:32 +01:00
cpu.c arm64: core support 2014-01-09 16:08:44 +01:00
exceptions.S arm64: core support 2014-01-09 16:08:44 +01:00
generic_timer.c arm64: core support 2014-01-09 16:08:44 +01:00
Kconfig kconfig: armv8: move CONFIG_ARM64 to Kconfig 2014-09-16 12:24:00 -04:00
Makefile arm64 patch: gicv3 support 2014-04-08 00:15:12 +02:00
start.S Arm64 fix a bug of vbar_el3 initialization 2014-05-25 15:26:00 +02:00
tlb.S arm64: core support 2014-01-09 16:08:44 +01:00
transition.S armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
u-boot.lds arm64: core support 2014-01-09 16:08:44 +01:00