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https://github.com/brain-hackers/u-boot-brain
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a2927e09bc
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
34 lines
573 B
C
34 lines
573 B
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pnp_def.h>
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static void pnp_enter_conf_state(u16 dev)
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{
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u16 port = dev >> 8;
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outb(0x55, port);
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}
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static void pnp_exit_conf_state(u16 dev)
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{
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u16 port = dev >> 8;
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outb(0xaa, port);
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}
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void lpc47m_enable_serial(u16 dev, u16 iobase)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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