mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-13 00:03:26 +09:00
![Kever Yang](/assets/img/avatar_default.png)
Move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file later for all rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up header-list to not break FASTBOOT:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
|
|
*/
|
|
#include <asm/io.h>
|
|
#include <asm/arch-rockchip/grf_rk322x.h>
|
|
#include <asm/arch-rockchip/hardware.h>
|
|
|
|
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
|
|
void board_debug_uart_init(void)
|
|
{
|
|
#define GRF_BASE 0x11000000
|
|
static struct rk322x_grf * const grf = (void *)GRF_BASE;
|
|
enum {
|
|
GPIO1B2_SHIFT = 4,
|
|
GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
|
|
GPIO1B2_GPIO = 0,
|
|
GPIO1B2_UART1_SIN,
|
|
GPIO1B2_UART21_SIN,
|
|
|
|
GPIO1B1_SHIFT = 2,
|
|
GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
|
|
GPIO1B1_GPIO = 0,
|
|
GPIO1B1_UART1_SOUT,
|
|
GPIO1B1_UART21_SOUT,
|
|
};
|
|
enum {
|
|
CON_IOMUX_UART2SEL_SHIFT = 8,
|
|
CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
|
|
CON_IOMUX_UART2SEL_2 = 0,
|
|
CON_IOMUX_UART2SEL_21,
|
|
};
|
|
|
|
/* Enable early UART2 channel 1 on the RK322x */
|
|
rk_clrsetreg(&grf->gpio1b_iomux,
|
|
GPIO1B1_MASK | GPIO1B2_MASK,
|
|
GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
|
|
GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
|
|
/* Set channel C as UART2 input */
|
|
rk_clrsetreg(&grf->con_iomux,
|
|
CON_IOMUX_UART2SEL_MASK,
|
|
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
|
|
}
|
|
#endif
|