mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
246 lines
4.7 KiB
C
246 lines
4.7 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <linux/mtd/doc2000.h>
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#include <watchdog.h>
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#include <pci.h>
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#include "hardware.h"
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#include "pcippc2.h"
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#include "sconsole.h"
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#include "fpga_serial.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_WATCHDOG)
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static int pcippc2_wdt_init_done = 0;
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void pcippc2_wdt_init (void);
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#endif
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/* Check board identity
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*/
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int checkboard (void)
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{
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#ifdef CONFIG_PCIPPC2
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puts ("Board: Gespac PCIPPC-2\n");
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#else
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puts ("Board: Gespac PCIPPC-6\n");
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#endif
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return 0;
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}
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/* RAM size is stored in CPC0_RGBAN1
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*/
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u32 pcippc2_sdram_size (void)
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{
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return in32 (REG (CPC0, RGBAN1));
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}
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long initdram (int board_type)
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{
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return cpc710_ram_init ();
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}
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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out32 (REG (CPC0, SPOR), 0);
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iobarrier_rw ();
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while (1);
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/* notreached */
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return (-1);
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}
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int board_early_init_f (void)
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{
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out32 (REG (CPC0, RSTR), 0xC0000000);
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iobarrier_rw ();
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out32 (REG (CPC0, RSTR), 0xF0000000);
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iobarrier_rw ();
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out32 (REG (CPC0, UCTL), 0x00F80000);
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out32 (REG (CPC0, SIOC0), 0x30000000);
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out32 (REG (CPC0, ABCNTL), 0x00000000);
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out32 (REG (CPC0, SESR), 0x00000000);
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out32 (REG (CPC0, SEAR), 0x00000000);
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/* Detect IBM Avignon CPC710 Revision */
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if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
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out32 (REG (CPC0, PGCHP), 0xA0000040);
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else
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out32 (REG (CPC0, PGCHP), 0x80800040);
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out32 (REG (CPC0, ATAS), 0x709C2508);
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iobarrier_rw ();
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return 0;
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}
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void after_reloc (ulong dest_addr)
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{
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/* Jump to the main U-Boot board init code
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*/
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board_init_r ((gd_t *)gd, dest_addr);
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}
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int misc_init_r (void)
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{
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pcippc2_fpga_init ();
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pcippc2_cpci3264_init ();
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#if defined(CONFIG_WATCHDOG)
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pcippc2_wdt_init ();
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#endif
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fpga_serial_init (sconsole_get_baudrate ());
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sconsole_putc = fpga_serial_putc;
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sconsole_puts = fpga_serial_puts;
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sconsole_getc = fpga_serial_getc;
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sconsole_tstc = fpga_serial_tstc;
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sconsole_setbrg = fpga_serial_setbrg;
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sconsole_flush ();
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return (0);
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}
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void pci_init_board (void)
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{
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cpc710_pci_init ();
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/* FPGA requires no retry timeouts to be enabled
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*/
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cpc710_pci_enable_timeout ();
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}
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void doc_init (void)
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{
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doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
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}
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void pcippc2_cpci3264_init (void)
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{
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pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
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if (bdf == -1)
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{
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puts("Unable to find FPGA !\n");
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hang();
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}
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if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
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/* 32-bits Compact PCI bus - LSB bit */
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{
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iobarrier_rw();
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out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */
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iobarrier_rw();
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}
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}
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#if defined(CONFIG_WATCHDOG)
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void pcippc2_wdt_init (void)
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{
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out16r (FPGA (WDT, PROG), 0xffff);
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out8 (FPGA (WDT, CTRL), 0x1);
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pcippc2_wdt_init_done = 1;
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}
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void pcippc2_wdt_done (void)
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{
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out8 (FPGA (WDT, CTRL), 0x0);
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pcippc2_wdt_init_done = 0;
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}
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void pcippc2_wdt_reset (void)
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{
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if (pcippc2_wdt_init_done == 1)
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out8 (FPGA (WDT, REFRESH), 0x56);
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}
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void watchdog_reset (void)
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{
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int re_enable = disable_interrupts ();
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pcippc2_wdt_reset ();
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if (re_enable)
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enable_interrupts ();
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}
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#if (CONFIG_COMMANDS & CFG_CMD_BSP)
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int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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switch (argc) {
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case 1:
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printf ("Watchdog timer status is %s\n",
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pcippc2_wdt_init_done == 1 ? "on" : "off");
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return 0;
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case 2:
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if (!strcmp(argv[1],"on")) {
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pcippc2_wdt_init();
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printf("Watchdog timer now is on\n");
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return 0;
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} else if (!strcmp(argv[1],"off")) {
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pcippc2_wdt_done();
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printf("Watchdog timer now is off\n");
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return 0;
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} else
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break;
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default:
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break;
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}
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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wd, 2, 1, do_wd,
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"wd - check and set watchdog\n",
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"on - switch watchDog on\n"
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"wd off - switch watchdog off\n"
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"wd - print current status\n"
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);
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#endif /* CFG_CMD_BSP */
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#endif /* CONFIG_WATCHDOG */
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