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409a07c9d7
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com> |
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| arm | ||
| avr32 | ||
| blackfin | ||
| i386 | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nios | ||
| nios2 | ||
| powerpc | ||
| sh | ||
| sparc | ||
| .gitignore | ||