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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
522 lines
14 KiB
C
522 lines
14 KiB
C
/*
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* Address map functions for Marvell EBU SoCs (Kirkwood, Armada
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* 370/XP, Dove, Orion5x and MV78xx0)
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*
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* Ported from the Barebox version to U-Boot by:
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* Stefan Roese <sr@denx.de>
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*
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* The Barebox version is:
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on mbus driver from Linux
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* (C) Copyright 2008 Marvell Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* The Marvell EBU SoCs have a configurable physical address space:
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* the physical address at which certain devices (PCIe, NOR, NAND,
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* etc.) sit can be configured. The configuration takes place through
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* two sets of registers:
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*
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* - One to configure the access of the CPU to the devices. Depending
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* on the families, there are between 8 and 20 configurable windows,
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* each can be use to create a physical memory window that maps to a
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* specific device. Devices are identified by a tuple (target,
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* attribute).
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*
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* - One to configure the access to the CPU to the SDRAM. There are
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* either 2 (for Dove) or 4 (for other families) windows to map the
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* SDRAM into the physical address space.
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*
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* This driver:
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*
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* - Reads out the SDRAM address decoding windows at initialization
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* time, and fills the mbus_dram_info structure with these
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* informations. The exported function mv_mbus_dram_info() allow
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* device drivers to get those informations related to the SDRAM
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* address decoding windows. This is because devices also have their
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* own windows (configured through registers that are part of each
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* device register space), and therefore the drivers for Marvell
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* devices have to configure those device -> SDRAM windows to ensure
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* that DMA works properly.
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*
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* - Provides an API for platform code or device drivers to
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* dynamically add or remove address decoding windows for the CPU ->
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* device accesses. This API is mvebu_mbus_add_window_by_id(),
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* mvebu_mbus_add_window_remap_by_id() and
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* mvebu_mbus_del_window().
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/log2.h>
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#include <linux/mbus.h>
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/* DDR target is the same on all platforms */
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#define TARGET_DDR 0
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/* CPU Address Decode Windows registers */
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#define WIN_CTRL_OFF 0x0000
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#define WIN_CTRL_ENABLE BIT(0)
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#define WIN_CTRL_TGT_MASK 0xf0
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#define WIN_CTRL_TGT_SHIFT 4
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#define WIN_CTRL_ATTR_MASK 0xff00
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#define WIN_CTRL_ATTR_SHIFT 8
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#define WIN_CTRL_SIZE_MASK 0xffff0000
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#define WIN_CTRL_SIZE_SHIFT 16
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#define WIN_BASE_OFF 0x0004
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#define WIN_BASE_LOW 0xffff0000
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#define WIN_BASE_HIGH 0xf
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_LOW 0xffff0000
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#define WIN_REMAP_HI_OFF 0x000c
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#define ATTR_HW_COHERENCY (0x1 << 4)
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_BASE_CS_HIGH_MASK 0xf
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#define DDR_BASE_CS_LOW_MASK 0xff000000
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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#define DDR_SIZE_ENABLED BIT(0)
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#define DDR_SIZE_CS_MASK 0x1c
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#define DDR_SIZE_CS_SHIFT 2
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#define DDR_SIZE_MASK 0xff000000
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#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
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struct mvebu_mbus_state;
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struct mvebu_mbus_soc_data {
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unsigned int num_wins;
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unsigned int num_remappable_wins;
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unsigned int (*win_cfg_offset)(const int win);
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void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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};
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struct mvebu_mbus_state mbus_state
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__attribute__ ((section(".data")));
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static struct mbus_dram_target_info mbus_dram_info
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__attribute__ ((section(".data")));
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/*
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* Functions to manipulate the address decoding windows
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*/
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static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
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int win, int *enabled, u64 *base,
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u32 *size, u8 *target, u8 *attr,
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u64 *remap)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 basereg = readl(addr + WIN_BASE_OFF);
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u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
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if (!(ctrlreg & WIN_CTRL_ENABLE)) {
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*enabled = 0;
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return;
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}
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*enabled = 1;
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*base = ((u64)basereg & WIN_BASE_HIGH) << 32;
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*base |= (basereg & WIN_BASE_LOW);
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*size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
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if (target)
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*target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
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if (attr)
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*attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
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if (remap) {
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if (win < mbus->soc->num_remappable_wins) {
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u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
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u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
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*remap = ((u64)remap_hi << 32) | remap_low;
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} else {
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*remap = 0;
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}
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}
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}
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static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
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int win)
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{
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void __iomem *addr;
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addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (win < mbus->soc->num_remappable_wins) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/* Checks whether the given window number is available */
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static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
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const int win)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 ctrl = readl(addr + WIN_CTRL_OFF);
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return !(ctrl & WIN_CTRL_ENABLE);
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}
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/*
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* Checks whether the given (base, base+size) area doesn't overlap an
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* existing region
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*/
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static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size,
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u8 target, u8 attr)
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{
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u64 end = (u64)base + size;
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int win;
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for (win = 0; win < mbus->soc->num_wins; win++) {
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u64 wbase, wend;
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u32 wsize;
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u8 wtarget, wattr;
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int enabled;
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mvebu_mbus_read_window(mbus, win,
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&enabled, &wbase, &wsize,
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&wtarget, &wattr, NULL);
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if (!enabled)
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continue;
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wend = wbase + wsize;
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/*
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* Check if the current window overlaps with the
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* proposed physical range
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*/
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if ((u64)base < wend && end > wbase)
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return 0;
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/*
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* Check if target/attribute conflicts
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*/
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if (target == wtarget && attr == wattr)
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return 0;
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}
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return 1;
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}
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static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size)
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{
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int win;
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for (win = 0; win < mbus->soc->num_wins; win++) {
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u64 wbase;
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u32 wsize;
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int enabled;
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mvebu_mbus_read_window(mbus, win,
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&enabled, &wbase, &wsize,
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NULL, NULL, NULL);
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if (!enabled)
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continue;
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if (base == wbase && size == wsize)
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return win;
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}
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return -ENODEV;
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}
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static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
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int win, phys_addr_t base, size_t size,
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phys_addr_t remap, u8 target,
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u8 attr)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 ctrl, remap_addr;
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ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
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(attr << WIN_CTRL_ATTR_SHIFT) |
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(target << WIN_CTRL_TGT_SHIFT) |
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WIN_CTRL_ENABLE;
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writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (win < mbus->soc->num_remappable_wins) {
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if (remap == MVEBU_MBUS_NO_REMAP)
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remap_addr = base;
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else
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remap_addr = remap;
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writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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return 0;
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}
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static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size,
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phys_addr_t remap, u8 target,
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u8 attr)
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{
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int win;
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if (remap == MVEBU_MBUS_NO_REMAP) {
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for (win = mbus->soc->num_remappable_wins;
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win < mbus->soc->num_wins; win++)
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if (mvebu_mbus_window_is_free(mbus, win))
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return mvebu_mbus_setup_window(mbus, win, base,
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size, remap,
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target, attr);
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}
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for (win = 0; win < mbus->soc->num_wins; win++)
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if (mvebu_mbus_window_is_free(mbus, win))
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return mvebu_mbus_setup_window(mbus, win, base, size,
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remap, target, attr);
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return -ENOMEM;
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}
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/*
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* SoC-specific functions and definitions
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*/
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static unsigned int armada_370_xp_mbus_win_offset(int win)
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{
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/* The register layout is a bit annoying and the below code
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* tries to cope with it.
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* - At offset 0x0, there are the registers for the first 8
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* windows, with 4 registers of 32 bits per window (ctrl,
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* base, remap low, remap high)
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* - Then at offset 0x80, there is a hole of 0x10 bytes for
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* the internal registers base address and internal units
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* sync barrier register.
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* - Then at offset 0x90, there the registers for 12
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* windows, with only 2 registers of 32 bits per window
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* (ctrl, base).
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*/
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if (win < 8)
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return win << 4;
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else
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return 0x90 + ((win - 8) << 3);
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}
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static unsigned int orion5x_mbus_win_offset(int win)
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{
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return win << 4;
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}
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static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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int i;
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int cs;
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mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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/*
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* We only take care of entries for which the chip
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* select is enabled, and that don't have high base
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* address bits set (devices can only access the first
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* 32 bits of the memory).
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*/
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if ((size & DDR_SIZE_ENABLED) &&
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!(base & DDR_BASE_CS_HIGH_MASK)) {
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struct mbus_dram_window *w;
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w = &mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & DDR_BASE_CS_LOW_MASK;
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w->size = (size | ~DDR_SIZE_MASK) + 1;
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}
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}
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mbus_dram_info.num_cs = cs;
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}
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static const struct mvebu_mbus_soc_data
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armada_370_xp_mbus_data __maybe_unused = {
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.num_wins = 20,
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.num_remappable_wins = 8,
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.win_cfg_offset = armada_370_xp_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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static const struct mvebu_mbus_soc_data
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kirkwood_mbus_data __maybe_unused = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion5x_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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/*
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* Public API of the driver
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*/
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const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
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{
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return &mbus_dram_info;
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}
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int mvebu_mbus_add_window_remap_by_id(unsigned int target,
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unsigned int attribute,
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phys_addr_t base, size_t size,
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phys_addr_t remap)
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{
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struct mvebu_mbus_state *s = &mbus_state;
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if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
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printf("Cannot add window '%x:%x', conflicts with another window\n",
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target, attribute);
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return -EINVAL;
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}
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return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
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}
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int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
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phys_addr_t base, size_t size)
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{
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return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
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size, MVEBU_MBUS_NO_REMAP);
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}
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int mvebu_mbus_del_window(phys_addr_t base, size_t size)
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{
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int win;
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win = mvebu_mbus_find_window(&mbus_state, base, size);
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if (win < 0)
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return win;
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mvebu_mbus_disable_window(&mbus_state, win);
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return 0;
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}
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static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
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phys_addr_t *base)
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{
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int win;
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*base = 0xffffffff;
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for (win = 0; win < mbus->soc->num_wins; win++) {
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u64 wbase;
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u32 wsize;
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u8 wtarget, wattr;
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int enabled;
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mvebu_mbus_read_window(mbus, win,
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&enabled, &wbase, &wsize,
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&wtarget, &wattr, NULL);
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if (!enabled)
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continue;
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if (wbase < *base)
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*base = wbase;
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}
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}
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static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
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{
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phys_addr_t base;
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u32 val;
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u32 size;
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/* Set MBUS bridge base/ctrl */
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mvebu_mbus_get_lowest_base(&mbus_state, &base);
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size = 0xffffffff - base + 1;
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if (!is_power_of_2(size)) {
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/* Round up to next power of 2 */
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size = 1 << (ffs(base) + 1);
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base = 0xffffffff - size + 1;
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}
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/* Now write base and size */
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writel(base, MBUS_BRIDGE_WIN_BASE_REG);
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/* Align window size to 64KiB */
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val = (size / (64 << 10)) - 1;
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writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
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}
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int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
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u32 base, u32 size, u8 target, u8 attr)
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{
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if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
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printf("Cannot add window '%04x:%04x', conflicts with another window\n",
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target, attr);
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return -EBUSY;
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}
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/*
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* In U-Boot we first try to add the mbus window to the remap windows.
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* If this fails, lets try to add the windows to the non-remap windows.
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*/
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if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
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if (mvebu_mbus_alloc_window(mbus, base, size,
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MVEBU_MBUS_NO_REMAP, target, attr))
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return -ENOMEM;
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}
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/*
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* Re-configure the mbus bridge registers each time this function
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* is called. Since it may get called from the board code in
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* later boot stages as well.
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*/
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mvebu_config_mbus_bridge(mbus);
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return 0;
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}
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int mvebu_mbus_probe(struct mbus_win windows[], int count)
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{
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int win;
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int ret;
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int i;
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#if defined(CONFIG_KIRKWOOD)
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mbus_state.soc = &kirkwood_mbus_data;
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#endif
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#if defined(CONFIG_ARCH_MVEBU)
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mbus_state.soc = &armada_370_xp_mbus_data;
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#endif
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mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
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mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
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|
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for (win = 0; win < mbus_state.soc->num_wins; win++)
|
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mvebu_mbus_disable_window(&mbus_state, win);
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|
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mbus_state.soc->setup_cpu_target(&mbus_state);
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|
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/* Setup statically declared windows in the DT */
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for (i = 0; i < count; i++) {
|
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u32 base, size;
|
|
u8 target, attr;
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|
|
|
target = windows[i].target;
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attr = windows[i].attr;
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base = windows[i].base;
|
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size = windows[i].size;
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ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
|
|
if (ret < 0)
|
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return ret;
|
|
}
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|
|
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return 0;
|
|
}
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