mirror of
https://github.com/brain-hackers/u-boot-brain
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71cb3d7c78
Allow optionally bringing up the Apalis type specific 4 lane PCIe port as well as the PCIe switch as found on the Apalis Evaluation board. In order to avoid violating the PCIe reset timing do this by overriding the tegra_pcie_board_port_reset() function. Note however that both the Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe port are also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
40 lines
837 B
Plaintext
40 lines
837 B
Plaintext
if TARGET_APALIS_T30
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config SYS_BOARD
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default "apalis_t30"
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config SYS_VENDOR
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default "toradex"
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config SYS_CONFIG_NAME
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default "apalis_t30"
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config TDX_CFG_BLOCK
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default y
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config TDX_HAVE_MMC
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default y
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config TDX_CFG_BLOCK_DEV
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default "0"
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config TDX_CFG_BLOCK_PART
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default "1"
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# Toradex config block in eMMC, at the end of 1st "boot sector"
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config TDX_CFG_BLOCK_OFFSET
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default "-512"
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config APALIS_T30_PCIE_EVALBOARD_INIT
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bool "Apalis Evaluation Board PCIe Initialisation"
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help
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Bring up the Apalis type specific 4 lane PCIe port as well as the
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Apalis PCIe port with the PCIe switch as found on the Apalis
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Evaluation board. Note that by default both those ports are also left
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disabled in the device tree which needs changing as well for this to
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actually work.
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source "board/toradex/common/Kconfig"
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endif
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