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https://github.com/brain-hackers/u-boot-brain
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a9a84480f4
Certain parts of msmc sram can be used by DMSC or can be marked as L3 cache. Since the available size can vary, changing DT every time the size varies might be painful. So, query this information using TISCI cmd and fixup the DT for kernel. Fixing up DT does the following: - Create a sram node if not available - update the reg property with available size - update ranges property - loop through available sub nodes and delete it if: - mentioned size is out if available range - subnode represents l3 cache or dmsc usage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
16 lines
456 B
C
16 lines
456 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Andreas Dannenberg <dannenberg@ti.com>
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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void sdelay(unsigned long loops);
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u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
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u32 bound);
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struct ti_sci_handle *get_ti_sci_handle(void);
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
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#endif
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