Siew Chin Lim 404a98b0a4 arm: socfpga: Changed to store QSPI reference clock in kHz ... Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>		2021-04-08 17:29:12 +08:00
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mach	arm: socfpga: Changed to store QSPI reference clock in kHz	2021-04-08 17:29:12 +08:00