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* Add PCI support for SL8245 board * Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) or 1 x AM29LV652 (two LV065 in one chip = 16 MB); Run IPB at 133 Mhz; adjust the MII clock frequency accordingly * Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) to allow for more accurate baudrate settings (error now 0.7% at 115 kbps, instead of 3.5% before) * Patch by Andreas Mohr, 4 Sep 2003: Fix a lot of spelling errors
737 lines
25 KiB
Plaintext
737 lines
25 KiB
Plaintext
Power-On-Self-Test support in U-Boot
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------------------------------------
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This project is to support Power-On-Self-Test (POST) in U-Boot.
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1. High-level requirements
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The key requirements for this project are as follows:
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1) The project shall develop a flexible framework for implementing
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and running Power-On-Self-Test in U-Boot. This framework shall
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possess the following features:
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o) Extensibility
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The framework shall allow adding/removing/replacing POST tests.
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Also, standalone POST tests shall be supported.
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o) Configurability
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The framework shall allow run-time configuration of the lists
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of tests running on normal/power-fail booting.
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o) Controllability
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The framework shall support manual running of the POST tests.
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2) The results of tests shall be saved so that it will be possible to
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retrieve them from Linux.
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3) The following POST tests shall be developed for MPC823E-based
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boards:
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o) CPU test
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o) Cache test
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o) Memory test
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o) Ethernet test
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o) Serial channels test
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o) Watchdog timer test
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o) RTC test
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o) I2C test
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o) SPI test
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o) USB test
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4) The LWMON board shall be used for reference.
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2. Design
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This section details the key points of the design for the project.
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The whole project can be divided into two independent tasks:
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enhancing U-Boot/Linux to provide a common framework for running POST
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tests and developing such tests for particular hardware.
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2.1. Hardware-independent POST layer
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A new optional module will be added to U-Boot, which will run POST
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tests and collect their results at boot time. Also, U-Boot will
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support running POST tests manually at any time by executing a
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special command from the system console.
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The list of available POST tests will be configured at U-Boot build
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time. The POST layer will allow the developer to add any custom POST
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tests. All POST tests will be divided into the following groups:
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1) Tests running on power-on booting only
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This group will contain those tests that run only once on
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power-on reset (e.g. watchdog test)
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2) Tests running on normal booting only
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This group will contain those tests that do not take much
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time and can be run on the regular basis (e.g. CPU test)
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3) Tests running in special "slow test mode" only
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This group will contain POST tests that consume much time
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and cannot be run regularly (e.g. strong memory test, I2C test)
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4) Manually executed tests
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This group will contain those tests that can be run manually.
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If necessary, some tests may belong to several groups simultaneously.
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For example, SDRAM test may run in both normal and "slow test" mode.
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In normal mode, SDRAM test may perform a fast superficial memory test
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only, while running in slow test mode it may perform a full memory
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check-up.
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Also, all tests will be discriminated by the moment they run at.
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Specifically, the following groups will be singled out:
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1) Tests running before relocating to RAM
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These tests will run immediately after initializing RAM
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as to enable modifying it without taking care of its
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contents. Basically, this group will contain memory tests
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only.
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2) Tests running after relocating to RAM
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These tests will run immediately before entering the main
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loop as to guarantee full hardware initialization.
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The POST layer will also distinguish a special group of tests that
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may cause system rebooting (e.g. watchdog test). For such tests, the
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layer will automatically detect rebooting and will notify the test
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about it.
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2.1.1. POST layer interfaces
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This section details the interfaces between the POST layer and the
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rest of U-Boot.
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The following flags will be defined:
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#define POST_POWERON 0x01 /* test runs on power-on booting */
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#define POST_NORMAL 0x02 /* test runs on normal booting */
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#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
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#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
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#define POST_ROM 0x100 /* test runs in ROM */
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#define POST_RAM 0x200 /* test runs in RAM */
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#define POST_MANUAL 0x400 /* test can be executed manually */
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#define POST_REBOOT 0x800 /* test may cause rebooting */
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#define POST_PREREL 0x1000 /* test runs before relocation */
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The POST layer will export the following interface routines:
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o) int post_run(bd_t *bd, char *name, int flags);
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This routine will run the test (or the group of tests) specified
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by the name and flag arguments. More specifically, if the name
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argument is not NULL, the test with this name will be performed,
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otherwise all tests running in ROM/RAM (depending on the flag
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argument) will be executed. This routine will be called at least
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twice with name set to NULL, once from board_init_f() and once
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from board_init_r(). The flags argument will also specify the
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mode the test is executed in (power-on, normal, power-fail,
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manual).
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o) void post_reloc(ulong offset);
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This routine will be called from board_init_r() and will
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relocate the POST test table.
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o) int post_info(char *name);
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This routine will print the list of all POST tests that can be
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executed manually if name is NULL, and the description of a
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particular test if name is not NULL.
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o) int post_log(char *format, ...);
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This routine will be called from POST tests to log their
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results. Basically, this routine will print the results to
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stderr. The format of the arguments and the return value
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will be identical to the printf() routine.
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Also, the following board-specific routines will be called from the
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U-Boot common code:
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o) int board_power_mode(void)
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This routine will return the mode the system is running in
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(POST_POWERON, POST_NORMAL or POST_SHUTDOWN).
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o) void board_poweroff(void)
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This routine will turn off the power supply of the board. It
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will be called on power-fail booting after running all POST
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tests.
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o) int post_hotkeys_pressed(gd_t *gd)
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This routine will scan the keyboard to detect if a magic key
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combination has been pressed, or otherwise detect if the
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power-on long-running tests shall be executed or not ("normal"
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versus "slow" test mode).
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The list of available POST tests be kept in the post_tests array
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filled at U-Boot build time. The format of entry in this array will
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be as follows:
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struct post_test {
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char *name;
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char *cmd;
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char *desc;
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int flags;
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int (*test)(bd_t *bd, int flags);
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};
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o) name
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This field will contain a short name of the test, which will be
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used in logs and on listing POST tests (e.g. CPU test).
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o) cmd
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This field will keep a name for identifying the test on manual
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testing (e.g. cpu). For more information, refer to section
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"Command line interface".
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o) desc
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This field will contain a detailed description of the test,
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which will be printed on user request. For more information, see
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section "Command line interface".
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o) flags
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This field will contain a combination of the bit flags described
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above, which will specify the mode the test is running in
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(power-on, normal, power-fail or manual mode), the moment it
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should be run at (before or after relocating to RAM), whether it
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can cause system rebooting or not.
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o) test
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This field will contain a pointer to the routine that will
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perform the test, which will take 2 arguments. The first
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argument will be a pointer to the board info structure, while
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the second will be a combination of bit flags specifying the
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mode the test is running in (POST_POWERON, POST_NORMAL,
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POST_SLOWTEST, POST_MANUAL) and whether the last execution of
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the test caused system rebooting (POST_REBOOT). The routine will
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return 0 on successful execution of the test, and 1 if the test
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failed.
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The lists of the POST tests that should be run at power-on/normal/
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power-fail booting will be kept in the environment. Namely, the
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following environment variables will be used: post_poweron,
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powet_normal, post_slowtest.
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2.1.2. Test results
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The results of tests will be collected by the POST layer. The POST
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log will have the following format:
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...
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--------------------------------------------
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START <name>
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<test-specific output>
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[PASSED|FAILED]
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--------------------------------------------
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...
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Basically, the results of tests will be printed to stderr. This
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feature may be enhanced in future to spool the log to a serial line,
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save it in non-volatile RAM (NVRAM), transfer it to a dedicated
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storage server and etc.
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2.1.3. Integration issues
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All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
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This macro will be defined in the config_<board>.h file for those
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boards that need POST. The CONFIG_POST macro will contain the list of
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POST tests for the board. The macro will have the format of array
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composed of post_test structures:
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#define CONFIG_POST \
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{
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"On-board peripherals test", "board", \
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" This test performs full check-up of the " \
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"on-board hardware.", \
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POST_RAM | POST_SLOWTEST, \
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&board_post_test \
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}
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A new file, post.h, will be created in the include/ directory. This
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file will contain common POST declarations and will define a set of
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macros that will be reused for defining CONFIG_POST. As an example,
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the following macro may be defined:
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#define POST_CACHE \
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{
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"Cache test", "cache", \
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" This test verifies the CPU cache operation.", \
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POST_RAM | POST_NORMAL, \
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&cache_post_test \
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}
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A new subdirectory will be created in the U-Boot root directory. It
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will contain the source code of the POST layer and most of POST
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tests. Each POST test in this directory will be placed into a
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separate file (it will be needed for building standalone tests). Some
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POST tests (mainly those for testing peripheral devices) will be
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located in the source files of the drivers for those devices. This
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way will be used only if the test subtantially uses the driver.
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2.1.4. Standalone tests
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The POST framework will allow to develop and run standalone tests. A
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user-space library will be developed to provide the POST interface
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functions to standalone tests.
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2.1.5. Command line interface
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A new command, diag, will be added to U-Boot. This command will be
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used for listing all available hardware tests, getting detailed
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descriptions of them and running these tests.
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More specifically, being run without any arguments, this command will
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print the list of all available hardware tests:
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=> diag
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Available hardware tests:
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cache - cache test
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cpu - CPU test
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enet - SCC/FCC ethernet test
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Use 'diag [<test1> [<test2>]] ... ' to get more info.
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Use 'diag run [<test1> [<test2>]] ... ' to run tests.
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=>
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If the first argument to the diag command is not 'run', detailed
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descriptions of the specified tests will be printed:
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=> diag cpu cache
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cpu - CPU test
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This test verifies the arithmetic logic unit of CPU.
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cache - cache test
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This test verifies the CPU cache operation.
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=>
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If the first argument to diag is 'run', the specified tests will be
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executed. If no tests are specified, all available tests will be
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executed.
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It will be prohibited to execute tests running in ROM manually. The
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'diag' command will not display such tests and/or run them.
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2.1.6. Power failure handling
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The Linux kernel will be modified to detect power failures and
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automatically reboot the system in such cases. It will be assumed
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that the power failure causes a system interrupt.
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To perform correct system shutdown, the kernel will register a
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handler of the power-fail IRQ on booting. Being called, the handler
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will run /sbin/reboot using the call_usermodehelper() routine.
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/sbin/reboot will automatically bring the system down in a secure
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way. This feature will be configured in/out from the kernel
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configuration file.
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The POST layer of U-Boot will check whether the system runs in
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power-fail mode. If it does, the system will be powered off after
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executing all hardware tests.
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2.1.7. Hazardous tests
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Some tests may cause system rebooting during their execution. For
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some tests, this will indicate a failure, while for the Watchdog
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test, this means successful operation of the timer.
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In order to support such tests, the following scheme will be
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implemented. All the tests that may cause system rebooting will have
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the POST_REBOOT bit flag set in the flag field of the correspondent
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post_test structure. Before starting tests marked with this bit flag,
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the POST layer will store an identification number of the test in a
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location in IMMR. On booting, the POST layer will check the value of
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this variable and if it is set will skip over the tests preceding the
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failed one. On second execution of the failed test, the POST_REBOOT
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bit flag will be set in the flag argument to the test routine. This
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will allow to detect system rebooting on the previous iteration. For
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example, the watchdog timer test may have the following
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declaration/body:
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...
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#define POST_WATCHDOG \
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{
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"Watchdog timer test", "watchdog", \
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" This test checks the watchdog timer.", \
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POST_RAM | POST_POWERON | POST_REBOOT, \
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&watchdog_post_test \
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}
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...
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...
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int watchdog_post_test(bd_t *bd, int flags)
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{
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unsigned long start_time;
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if (flags & POST_REBOOT) {
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/* Test passed */
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return 0;
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} else {
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/* disable interrupts */
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disable_interrupts();
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/* 10-second delay */
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...
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/* if we've reached this, the watchdog timer does not work */
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enable_interrupts();
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return 1;
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}
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}
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...
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2.2. Hardware-specific details
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This project will also develop a set of POST tests for MPC8xx- based
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systems. This section provides technical details of how it will be
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done.
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2.2.1. Generic PPC tests
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The following generic POST tests will be developed:
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o) CPU test
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This test will check the arithmetic logic unit (ALU) of CPU. The
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test will take several milliseconds and will run on normal
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booting.
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o) Cache test
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This test will verify the CPU cache (L1 cache). The test will
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run on normal booting.
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o) Memory test
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This test will examine RAM and check it for errors. The test
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will always run on booting. On normal booting, only a limited
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amount of RAM will be checked. On power-fail booting a fool
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memory check-up will be performed.
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2.2.1.1. CPU test
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This test will verify the following ALU instructions:
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o) Condition register istructions
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This group will contain: mtcrf, mfcr, mcrxr, crand, crandc,
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cror, crorc, crxor, crnand, crnor, creqv, mcrf.
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The mtcrf/mfcr instructions will be tested by loading different
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values into the condition register (mtcrf), moving its value to
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a general-purpose register (mfcr) and comparing this value with
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the expected one. The mcrxr instruction will be tested by
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loading a fixed value into the XER register (mtspr), moving XER
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value to the condition register (mcrxr), moving it to a
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general-purpose register (mfcr) and comparing the value of this
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register with the expected one. The rest of instructions will be
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tested by loading a fixed value into the condition register
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(mtcrf), executing each instruction several times to modify all
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4-bit condition fields, moving the value of the conditional
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register to a general-purpose register (mfcr) and comparing it
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with the expected one.
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o) Integer compare instructions
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This group will contain: cmp, cmpi, cmpl, cmpli.
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To verify these instructions the test will run them with
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different combinations of operands, read the condition register
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value and compare it with the expected one. More specifically,
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the test will contain a pre-built table containing the
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description of each test case: the instruction, the values of
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the operands, the condition field to save the result in and the
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expected result.
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o) Arithmetic instructions
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This group will contain: add, addc, adde, addme, addze, subf,
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subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu,
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extsb, extsh.
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The test will contain a pre-built table of instructions,
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operands, expected results and expected states of the condition
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register. For each table entry, the test will cyclically use
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different sets of operand registers and result registers. For
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example, for instructions that use 3 registers on the first
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iteration r0/r1 will be used as operands and r2 for result. On
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the second iteration, r1/r2 will be used as operands and r3 as
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for result and so on. This will enable to verify all
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general-purpose registers.
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o) Logic instructions
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This group will contain: and, andc, andi, andis, or, orc, ori,
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oris, xor, xori, xoris, nand, nor, neg, eqv, cntlzw.
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The test scheme will be identical to that from the previous
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point.
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o) Shift instructions
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This group will contain: slw, srw, sraw, srawi, rlwinm, rlwnm,
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rlwimi
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The test scheme will be identical to that from the previous
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point.
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o) Branch instructions
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This group will contain: b, bl, bc.
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The first 2 instructions (b, bl) will be verified by jumping to
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a fixed address and checking whether control was transfered to
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that very point. For the bl instruction the value of the link
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register will be checked as well (using mfspr). To verify the bc
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instruction various combinations of the BI/BO fields, the CTR
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and the condition register values will be checked. The list of
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such combinations will be pre-built and linked in U-Boot at
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build time.
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o) Load/store instructions
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This group will contain: lbz(x)(u), lhz(x)(u), lha(x)(u),
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lwz(x)(u), stb(x)(u), sth(x)(u), stw(x)(u).
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All operations will be performed on a 16-byte array. The array
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will be 4-byte aligned. The base register will point to offset
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8. The immediate offset (index register) will range in [-8 ...
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+7]. The test cases will be composed so that they will not cause
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alignment exceptions. The test will contain a pre-built table
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describing all test cases. For store instructions, the table
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entry will contain: the instruction opcode, the value of the
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index register and the value of the source register. After
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executing the instruction, the test will verify the contents of
|
|
the array and the value of the base register (it must change for
|
|
"store with update" instructions). For load instructions, the
|
|
table entry will contain: the instruction opcode, the array
|
|
contents, the value of the index register and the expected value
|
|
of the destination register. After executing the instruction,
|
|
the test will verify the value of the destination register and
|
|
the value of the base register (it must change for "load with
|
|
update" instructions).
|
|
|
|
o) Load/store multiple/string instructions
|
|
|
|
|
|
The CPU test will run in RAM in order to allow run-time modification
|
|
of the code to reduce the memory footprint.
|
|
|
|
2.2.1.2 Special-Purpose Registers Tests
|
|
|
|
TBD.
|
|
|
|
2.2.1.3. Cache test
|
|
|
|
To verify the data cache operation the following test scenarios will
|
|
be used:
|
|
|
|
1) Basic test #1
|
|
|
|
- turn on the data cache
|
|
- switch the data cache to write-back or write-through mode
|
|
- invalidate the data cache
|
|
- write the negative pattern to a cached area
|
|
- read the area
|
|
|
|
The negative pattern must be read at the last step
|
|
|
|
2) Basic test #2
|
|
|
|
- turn on the data cache
|
|
- switch the data cache to write-back or write-through mode
|
|
- invalidate the data cache
|
|
- write the zero pattern to a cached area
|
|
- turn off the data cache
|
|
- write the negative pattern to the area
|
|
- turn on the data cache
|
|
- read the area
|
|
|
|
The negative pattern must be read at the last step
|
|
|
|
3) Write-through mode test
|
|
|
|
- turn on the data cache
|
|
- switch the data cache to write-through mode
|
|
- invalidate the data cache
|
|
- write the zero pattern to a cached area
|
|
- flush the data cache
|
|
- write the negative pattern to the area
|
|
- turn off the data cache
|
|
- read the area
|
|
|
|
The negative pattern must be read at the last step
|
|
|
|
4) Write-back mode test
|
|
|
|
- turn on the data cache
|
|
- switch the data cache to write-back mode
|
|
- invalidate the data cache
|
|
- write the negative pattern to a cached area
|
|
- flush the data cache
|
|
- write the zero pattern to the area
|
|
- invalidate the data cache
|
|
- read the area
|
|
|
|
The negative pattern must be read at the last step
|
|
|
|
To verify the instruction cache operation the following test
|
|
scenarios will be used:
|
|
|
|
1) Basic test #1
|
|
|
|
- turn on the instruction cache
|
|
- unlock the entire instruction cache
|
|
- invalidate the instruction cache
|
|
- lock a branch instruction in the instruction cache
|
|
- replace the branch instruction with "nop"
|
|
- jump to the branch instruction
|
|
- check that the branch instruction was executed
|
|
|
|
2) Basic test #2
|
|
|
|
- turn on the instruction cache
|
|
- unlock the entire instruction cache
|
|
- invalidate the instruction cache
|
|
- jump to a branch instruction
|
|
- check that the branch instruction was executed
|
|
- replace the branch instruction with "nop"
|
|
- invalidate the instruction cache
|
|
- jump to the branch instruction
|
|
- check that the "nop" instruction was executed
|
|
|
|
The CPU test will run in RAM in order to allow run-time modification
|
|
of the code.
|
|
|
|
2.2.1.4. Memory test
|
|
|
|
The memory test will verify RAM using sequential writes and reads
|
|
to/from RAM. Specifically, there will be several test cases that will
|
|
use different patterns to verify RAM. Each test case will first fill
|
|
a region of RAM with one pattern and then read the region back and
|
|
compare its contents with the pattern. The following patterns will be
|
|
used:
|
|
|
|
1) zero pattern (0x00000000)
|
|
2) negative pattern (0xffffffff)
|
|
3) checkerboard pattern (0x55555555, 0xaaaaaaaa)
|
|
4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32)))
|
|
5) address pattern (offset, ~offset)
|
|
|
|
Patterns #1, #2 will help to find unstable bits. Patterns #3, #4 will
|
|
be used to detect adherent bits, i.e. bits whose state may randomly
|
|
change if adjacent bits are modified. The last pattern will be used
|
|
to detect far-located errors, i.e. situations when writing to one
|
|
location modifies an area located far from it. Also, usage of the
|
|
last pattern will help to detect memory controller misconfigurations
|
|
when RAM represents a cyclically repeated portion of a smaller size.
|
|
|
|
Being run in normal mode, the test will verify only small 4Kb regions
|
|
of RAM around each 1Mb boundary. For example, for 64Mb RAM the
|
|
following areas will be verified: 0x00000000-0x00000800,
|
|
0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
|
|
0x04000000. If the test is run in power-fail mode, it will verify the
|
|
whole RAM.
|
|
|
|
The memory test will run in ROM before relocating U-Boot to RAM in
|
|
order to allow RAM modification without saving its contents.
|
|
|
|
2.2.2. Common tests
|
|
|
|
This section describes tests that are not based on any hardware
|
|
peculiarities and use common U-Boot interfaces only. These tests do
|
|
not need any modifications for porting them to another board/CPU.
|
|
|
|
2.2.2.1. I2C test
|
|
|
|
For verifying the I2C bus, a full I2C bus scanning will be performed
|
|
using the i2c_probe() routine. If any I2C device is found, the test
|
|
will be considered as passed, otherwise failed. This particular way
|
|
will be used because it provides the most common method of testing.
|
|
For example, using the internal loopback mode of the CPM I2C
|
|
controller for testing would not work on boards where the software
|
|
I2C driver (also known as bit-banged driver) is used.
|
|
|
|
2.2.2.2. Watchdog timer test
|
|
|
|
To test the watchdog timer the scheme mentioned above (refer to
|
|
section "Hazardous tests") will be used. Namely, this test will be
|
|
marked with the POST_REBOOT bit flag. On the first iteration, the
|
|
test routine will make a 10-second delay. If the system does not
|
|
reboot during this delay, the watchdog timer is not operational and
|
|
the test fails. If the system reboots, on the second iteration the
|
|
POST_REBOOT bit will be set in the flag argument to the test routine.
|
|
The test routine will check this bit and report a success if it is
|
|
set.
|
|
|
|
2.2.2.3. RTC test
|
|
|
|
The RTC test will use the rtc_get()/rtc_set() routines. The following
|
|
features will be verified:
|
|
|
|
o) Time uniformity
|
|
|
|
This will be verified by reading RTC in polling within a short
|
|
period of time (5-10 seconds).
|
|
|
|
o) Passing month boundaries
|
|
|
|
This will be checked by setting RTC to a second before a month
|
|
boundary and reading it after its passing the boundary. The test
|
|
will be performed for both leap- and nonleap-years.
|
|
|
|
2.2.3. MPC8xx peripherals tests
|
|
|
|
This project will develop a set of tests verifying the peripheral
|
|
units of MPC8xx processors. Namely, the following controllers of the
|
|
MPC8xx communication processor module (CPM) will be tested:
|
|
|
|
o) Serial Management Controllers (SMC)
|
|
|
|
o) Serial Communication Controllers (SCC)
|
|
|
|
2.2.3.1. Ethernet tests (SCC)
|
|
|
|
The internal (local) loopback mode will be used to test SCC. To do
|
|
that the controllers will be configured accordingly and several
|
|
packets will be transmitted. These tests may be enhanced in future to
|
|
use external loopback for testing. That will need appropriate
|
|
reconfiguration of the physical interface chip.
|
|
|
|
The test routines for the SCC ethernet tests will be located in
|
|
cpu/mpc8xx/scc.c.
|
|
|
|
2.2.3.2. UART tests (SMC/SCC)
|
|
|
|
To perform these tests the internal (local) loopback mode will be
|
|
used. The SMC/SCC controllers will be configured to connect the
|
|
transmitter output to the receiver input. After that, several bytes
|
|
will be transmitted. These tests may be enhanced to make to perform
|
|
"external" loopback test using a loopback cable. In this case, the
|
|
test will be executed manually.
|
|
|
|
The test routine for the SMC/SCC UART tests will be located in
|
|
cpu/mpc8xx/serial.c.
|
|
|
|
2.2.3.3. USB test
|
|
|
|
TBD
|
|
|
|
2.2.3.4. SPI test
|
|
|
|
TBD
|