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https://github.com/brain-hackers/u-boot-brain
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7873e9df8f
The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
183 lines
4.3 KiB
C
183 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: ARM64 MMU setup
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*
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* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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* Suman Anna <s-anna@ti.com>
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* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
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*
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#ifdef CONFIG_SOC_K3_AM6
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
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/* ToDo: Add 64bit IO */
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struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x02100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa2100000UL,
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.phys = 0xa2100000UL,
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.size = 0x5df00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = am654_mem_map;
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#endif /* CONFIG_SOC_K3_AM6 */
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#ifdef CONFIG_SOC_K3_J721E
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#ifdef CONFIG_TARGET_J721E_A72_EVM
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
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/* ToDo: Add 64bit IO */
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struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x1bc00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0xbbc00000UL,
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.phys = 0xbbc00000UL,
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.size = 0x44400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x4d80000000UL,
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.phys = 0x4d80000000UL,
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.size = 0x0002000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = j721e_mem_map;
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#endif /* CONFIG_TARGET_J721E_A72_EVM */
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#ifdef CONFIG_TARGET_J7200_A72_EVM
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
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/* ToDo: Add 64bit IO */
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struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x04800000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0xa4800000UL,
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.phys = 0xa4800000UL,
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.size = 0x5b800000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = j7200_mem_map;
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#endif /* CONFIG_TARGET_J7200_A72_EVM */
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#endif /* CONFIG_SOC_K3_J721E */
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