mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
5ec83561c4
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system image in case the primary one is corrupted. The user can force this boot mode as well by explicitly setting SRC GPR10 bit 30. This can be potentially useful when upgrading the bootloader itself. Expose this functionality to the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
141 lines
3.6 KiB
C
141 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/crm_regs.h>
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void init_aips(void)
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{
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struct aipstz_regs *aips1, *aips2, *aips3;
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips1->mprot0);
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writel(0x77777777, &aips1->mprot1);
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writel(0x77777777, &aips2->mprot0);
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writel(0x77777777, &aips2->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips1->opacr0);
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writel(0x00000000, &aips1->opacr1);
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writel(0x00000000, &aips1->opacr2);
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writel(0x00000000, &aips1->opacr3);
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writel(0x00000000, &aips1->opacr4);
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writel(0x00000000, &aips2->opacr0);
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writel(0x00000000, &aips2->opacr1);
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writel(0x00000000, &aips2->opacr2);
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr4);
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if (is_mx6ull() || is_mx6sx() || is_mx7()) {
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips3->mprot0);
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writel(0x77777777, &aips3->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips3->opacr0);
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writel(0x00000000, &aips3->opacr1);
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writel(0x00000000, &aips3->opacr2);
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writel(0x00000000, &aips3->opacr3);
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writel(0x00000000, &aips3->opacr4);
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}
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}
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void imx_wdog_disable_powerdown(void)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
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#ifdef CONFIG_MX7D
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struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
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#endif
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/* Write to the PDE (Power Down Enable) bit */
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writew(0, &wdog1->wmcr);
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writew(0, &wdog2->wmcr);
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if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
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writew(0, &wdog3->wmcr);
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#ifdef CONFIG_MX7D
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writew(0, &wdog4->wmcr);
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#endif
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}
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#define SRC_SCR_WARM_RESET_ENABLE 0
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void init_src(void)
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{
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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u32 val;
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/*
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* force warm reset sources to generate cold reset
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* for a more reliable restart
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*/
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val = readl(&src_regs->scr);
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val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
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writel(val, &src_regs->scr);
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}
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#ifdef CONFIG_CMD_BMODE
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void boot_mode_apply(unsigned cfg_val)
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{
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#ifdef CONFIG_MX6
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const u32 persist_sec = IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT;
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const u32 bmode = IMX6_SRC_GPR10_BMODE;
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#elif CONFIG_MX7
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const u32 persist_sec = IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT;
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const u32 bmode = IMX7_SRC_GPR10_BMODE;
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#endif
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned reg;
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if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
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clrbits_le32(&psrc->gpr10, persist_sec);
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else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
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setbits_le32(&psrc->gpr10, persist_sec);
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else {
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writel(cfg_val, &psrc->gpr9);
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reg = readl(&psrc->gpr10);
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if (cfg_val)
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reg |= bmode;
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else
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reg &= ~bmode;
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writel(reg, &psrc->gpr10);
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}
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}
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#endif
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#if defined(CONFIG_MX6)
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u32 imx6_src_get_boot_mode(void)
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{
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if (readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE)
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return readl(&src_base->gpr9);
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else
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return readl(&src_base->sbmr1);
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}
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#endif
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