659 lines
14 KiB
C
659 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass.h>
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#include <errno.h>
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#include <spl.h>
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#include <thermal.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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#include <asm/armv8/mmu.h>
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#include <asm/setup.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BT_PASSOVER_TAG 0x504F
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struct pass_over_info_t *get_pass_over_info(void)
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{
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struct pass_over_info_t *p =
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(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
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if (p->barker != BT_PASSOVER_TAG ||
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p->len != sizeof(struct pass_over_info_t))
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return NULL;
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return p;
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}
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int arch_cpu_init(void)
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{
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
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spl_save_restore_data();
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#endif
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#ifdef CONFIG_SPL_BUILD
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struct pass_over_info_t *pass_over;
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if (is_soc_rev(CHIP_REV_A)) {
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pass_over = get_pass_over_info();
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if (pass_over && pass_over->g_ap_mu == 0) {
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/*
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* When ap_mu is 0, means the U-Boot booted
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* from first container
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*/
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sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
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}
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}
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#endif
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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struct udevice *devp;
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int node, ret;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
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ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
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if (ret) {
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printf("could not get scu %d\n", ret);
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return ret;
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}
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if (is_imx8qm()) {
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ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
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SC_PM_PW_MODE_ON);
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if (ret)
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return ret;
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}
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return 0;
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}
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int print_bootinfo(void)
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{
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enum boot_device bt_dev = get_boot_device();
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puts("Boot: ");
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switch (bt_dev) {
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case SD1_BOOT:
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puts("SD0\n");
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break;
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case SD2_BOOT:
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puts("SD1\n");
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break;
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case SD3_BOOT:
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puts("SD2\n");
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break;
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case MMC1_BOOT:
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puts("MMC0\n");
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break;
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case MMC2_BOOT:
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puts("MMC1\n");
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break;
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case MMC3_BOOT:
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puts("MMC2\n");
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break;
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case FLEXSPI_BOOT:
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puts("FLEXSPI\n");
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break;
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case SATA_BOOT:
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puts("SATA\n");
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break;
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case NAND_BOOT:
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puts("NAND\n");
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break;
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case USB_BOOT:
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puts("USB\n");
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break;
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default:
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printf("Unknown device %u\n", bt_dev);
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break;
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}
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return 0;
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}
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enum boot_device get_boot_device(void)
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{
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enum boot_device boot_dev = SD1_BOOT;
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sc_rsrc_t dev_rsrc;
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sc_misc_get_boot_dev(-1, &dev_rsrc);
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switch (dev_rsrc) {
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case SC_R_SDHC_0:
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boot_dev = MMC1_BOOT;
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break;
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case SC_R_SDHC_1:
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boot_dev = SD2_BOOT;
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break;
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case SC_R_SDHC_2:
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boot_dev = SD3_BOOT;
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break;
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case SC_R_NAND:
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boot_dev = NAND_BOOT;
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break;
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case SC_R_FSPI_0:
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boot_dev = FLEXSPI_BOOT;
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break;
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case SC_R_SATA_0:
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boot_dev = SATA_BOOT;
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break;
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case SC_R_USB_0:
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case SC_R_USB_1:
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case SC_R_USB_2:
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boot_dev = USB_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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#ifdef CONFIG_SERIAL_TAG
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#define FUSE_UNIQUE_ID_WORD0 16
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#define FUSE_UNIQUE_ID_WORD1 17
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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sc_err_t err;
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u32 val1 = 0, val2 = 0;
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u32 word1, word2;
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if (!serialnr)
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return;
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word1 = FUSE_UNIQUE_ID_WORD0;
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word2 = FUSE_UNIQUE_ID_WORD1;
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err = sc_misc_otp_fuse_read(-1, word1, &val1);
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if (err != SC_ERR_NONE) {
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printf("%s fuse %d read error: %d\n", __func__, word1, err);
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return;
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}
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err = sc_misc_otp_fuse_read(-1, word2, &val2);
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if (err != SC_ERR_NONE) {
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printf("%s fuse %d read error: %d\n", __func__, word2, err);
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return;
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}
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serialnr->low = val1;
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serialnr->high = val2;
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}
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#endif /*CONFIG_SERIAL_TAG*/
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#ifdef CONFIG_ENV_IS_IN_MMC
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__weak int board_mmc_get_env_dev(int devno)
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{
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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int mmc_get_env_dev(void)
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{
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sc_rsrc_t dev_rsrc;
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int devno;
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sc_misc_get_boot_dev(-1, &dev_rsrc);
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switch (dev_rsrc) {
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case SC_R_SDHC_0:
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devno = 0;
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break;
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case SC_R_SDHC_1:
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devno = 1;
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break;
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case SC_R_SDHC_2:
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devno = 2;
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break;
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default:
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/* If not boot from sd/mmc, use default value */
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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return board_mmc_get_env_dev(devno);
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}
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#endif
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#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
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static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
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sc_faddr_t *addr_end)
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{
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sc_faddr_t start, end;
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int ret;
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bool owned;
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owned = sc_rm_is_memreg_owned(-1, mr);
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if (owned) {
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ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
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if (ret) {
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printf("Memreg get info failed, %d\n", ret);
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return -EINVAL;
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}
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debug("0x%llx -- 0x%llx\n", start, end);
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*addr_start = start;
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*addr_end = end;
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return 0;
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}
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return -EINVAL;
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}
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__weak void board_mem_get_layout(u64 *phys_sdram_1_start,
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u64 *phys_sdram_1_size,
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u64 *phys_sdram_2_start,
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u64 *phys_sdram_2_size)
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{
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*phys_sdram_1_start = PHYS_SDRAM_1;
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*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
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*phys_sdram_2_start = PHYS_SDRAM_2;
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*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
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}
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phys_size_t get_effective_memsize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, start_aligned;
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u64 phys_sdram_1_start, phys_sdram_1_size;
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u64 phys_sdram_2_start, phys_sdram_2_size;
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int err;
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board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
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&phys_sdram_2_start, &phys_sdram_2_size);
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end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start_aligned = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start_aligned > end)
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continue;
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/* Find the memory region runs the U-Boot */
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if (start >= phys_sdram_1_start && start <= end1 &&
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(start <= CONFIG_SYS_TEXT_BASE &&
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end >= CONFIG_SYS_TEXT_BASE)) {
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if ((end + 1) <=
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((sc_faddr_t)phys_sdram_1_start +
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phys_sdram_1_size))
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return (end - phys_sdram_1_start + 1);
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else
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return phys_sdram_1_size;
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}
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}
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}
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return phys_sdram_1_size;
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}
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int dram_init(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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u64 phys_sdram_1_start, phys_sdram_1_size;
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u64 phys_sdram_2_start, phys_sdram_2_size;
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int err;
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board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
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&phys_sdram_2_start, &phys_sdram_2_size);
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end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
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end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start > end)
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continue;
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if (start >= phys_sdram_1_start && start <= end1) {
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if ((end + 1) <= end1)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end1 - start;
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} else if (start >= phys_sdram_2_start &&
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start <= end2) {
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if ((end + 1) <= end2)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end2 - start;
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}
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}
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}
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/* If error, set to the default value */
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if (!gd->ram_size) {
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gd->ram_size = phys_sdram_1_size;
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gd->ram_size += phys_sdram_2_size;
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}
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return 0;
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}
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static void dram_bank_sort(int current_bank)
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{
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phys_addr_t start;
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phys_size_t size;
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while (current_bank > 0) {
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if (gd->bd->bi_dram[current_bank - 1].start >
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gd->bd->bi_dram[current_bank].start) {
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start = gd->bd->bi_dram[current_bank - 1].start;
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size = gd->bd->bi_dram[current_bank - 1].size;
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gd->bd->bi_dram[current_bank - 1].start =
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gd->bd->bi_dram[current_bank].start;
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gd->bd->bi_dram[current_bank - 1].size =
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gd->bd->bi_dram[current_bank].size;
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gd->bd->bi_dram[current_bank].start = start;
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gd->bd->bi_dram[current_bank].size = size;
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}
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current_bank--;
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}
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}
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int dram_init_banksize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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int i = 0;
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u64 phys_sdram_1_start, phys_sdram_1_size;
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u64 phys_sdram_2_start, phys_sdram_2_size;
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int err;
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board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
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&phys_sdram_2_start, &phys_sdram_2_size);
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end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
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end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
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for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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if (start > end) /* Small memory region, no use it */
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continue;
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if (start >= phys_sdram_1_start && start <= end1) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end1)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end1 - start;
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dram_bank_sort(i);
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i++;
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} else if (start >= phys_sdram_2_start && start <= end2) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end2)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end2 - start;
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dram_bank_sort(i);
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i++;
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}
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}
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}
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/* If error, set to the default value */
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if (!i) {
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gd->bd->bi_dram[0].start = phys_sdram_1_start;
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gd->bd->bi_dram[0].size = phys_sdram_1_size;
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gd->bd->bi_dram[1].start = phys_sdram_2_start;
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gd->bd->bi_dram[1].size = phys_sdram_2_size;
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}
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return 0;
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}
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static u64 get_block_attrs(sc_faddr_t addr_start)
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{
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u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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u64 phys_sdram_1_start, phys_sdram_1_size;
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u64 phys_sdram_2_start, phys_sdram_2_size;
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board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
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&phys_sdram_2_start, &phys_sdram_2_size);
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if ((addr_start >= phys_sdram_1_start &&
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addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
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(addr_start >= phys_sdram_2_start &&
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addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
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return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
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return attr;
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}
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static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
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{
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sc_faddr_t end1, end2;
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u64 phys_sdram_1_start, phys_sdram_1_size;
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u64 phys_sdram_2_start, phys_sdram_2_size;
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board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
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&phys_sdram_2_start, &phys_sdram_2_size);
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end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
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end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
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if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
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if ((addr_end + 1) > end1)
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return end1 - addr_start;
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} else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
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if ((addr_end + 1) > end2)
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return end2 - addr_start;
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}
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return (addr_end - addr_start + 1);
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}
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
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struct mm_region *mem_map = imx8_mem_map;
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void enable_caches(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end;
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int err, i;
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/* Create map for registers access from 0x1c000000 to 0x80000000*/
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imx8_mem_map[0].virt = 0x1c000000UL;
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imx8_mem_map[0].phys = 0x1c000000UL;
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imx8_mem_map[0].size = 0x64000000UL;
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imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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i = 1;
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for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
|
|
err = get_owned_memreg(mr, &start, &end);
|
|
if (!err) {
|
|
imx8_mem_map[i].virt = start;
|
|
imx8_mem_map[i].phys = start;
|
|
imx8_mem_map[i].size = get_block_size(start, end);
|
|
imx8_mem_map[i].attrs = get_block_attrs(start);
|
|
i++;
|
|
}
|
|
}
|
|
|
|
if (i < MAX_MEM_MAP_REGIONS) {
|
|
imx8_mem_map[i].size = 0;
|
|
imx8_mem_map[i].attrs = 0;
|
|
} else {
|
|
puts("Error, need more MEM MAP REGIONS reserved\n");
|
|
icache_enable();
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
|
|
debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
|
|
i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
|
|
imx8_mem_map[i].size, imx8_mem_map[i].attrs);
|
|
}
|
|
|
|
icache_enable();
|
|
dcache_enable();
|
|
}
|
|
|
|
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
|
u64 get_page_table_size(void)
|
|
{
|
|
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
|
|
u64 size = 0;
|
|
|
|
/*
|
|
* For each memory region, the max table size:
|
|
* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
|
|
*/
|
|
size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
|
|
|
|
/*
|
|
* We need to duplicate our page table once to have an emergency pt to
|
|
* resort to when splitting page tables later on
|
|
*/
|
|
size *= 2;
|
|
|
|
/*
|
|
* We may need to split page tables later on if dcache settings change,
|
|
* so reserve up to 4 (random pick) page tables for that.
|
|
*/
|
|
size += one_pt * 4;
|
|
|
|
return size;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_IMX8QM)
|
|
#define FUSE_MAC0_WORD0 452
|
|
#define FUSE_MAC0_WORD1 453
|
|
#define FUSE_MAC1_WORD0 454
|
|
#define FUSE_MAC1_WORD1 455
|
|
#elif defined(CONFIG_IMX8QXP)
|
|
#define FUSE_MAC0_WORD0 708
|
|
#define FUSE_MAC0_WORD1 709
|
|
#define FUSE_MAC1_WORD0 710
|
|
#define FUSE_MAC1_WORD1 711
|
|
#endif
|
|
|
|
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
|
{
|
|
u32 word[2], val[2] = {};
|
|
int i, ret;
|
|
|
|
if (dev_id == 0) {
|
|
word[0] = FUSE_MAC0_WORD0;
|
|
word[1] = FUSE_MAC0_WORD1;
|
|
} else {
|
|
word[0] = FUSE_MAC1_WORD0;
|
|
word[1] = FUSE_MAC1_WORD1;
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
|
|
if (ret < 0)
|
|
goto err;
|
|
}
|
|
|
|
mac[0] = val[0];
|
|
mac[1] = val[0] >> 8;
|
|
mac[2] = val[0] >> 16;
|
|
mac[3] = val[0] >> 24;
|
|
mac[4] = val[1];
|
|
mac[5] = val[1] >> 8;
|
|
|
|
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
|
|
__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
|
return;
|
|
err:
|
|
printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
|
|
}
|
|
|
|
u32 get_cpu_rev(void)
|
|
{
|
|
u32 id = 0, rev = 0;
|
|
int ret;
|
|
|
|
ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
|
|
if (ret)
|
|
return 0;
|
|
|
|
rev = (id >> 5) & 0xf;
|
|
id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
|
|
|
|
return (id << 12) | rev;
|
|
}
|
|
|
|
void board_boot_order(u32 *spl_boot_list)
|
|
{
|
|
spl_boot_list[0] = spl_boot_device();
|
|
|
|
if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
|
|
/* Check whether we own the flexspi0, if not, use NOR boot */
|
|
if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
|
|
spl_boot_list[0] = BOOT_DEVICE_NOR;
|
|
}
|
|
}
|
|
|
|
bool m4_parts_booted(void)
|
|
{
|
|
sc_rm_pt_t m4_parts[2];
|
|
int err;
|
|
|
|
err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
|
|
if (err) {
|
|
printf("%s get resource [%d] owner error: %d\n", __func__,
|
|
SC_R_M4_0_PID0, err);
|
|
return false;
|
|
}
|
|
|
|
if (sc_pm_is_partition_started(-1, m4_parts[0]))
|
|
return true;
|
|
|
|
if (is_imx8qm()) {
|
|
err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
|
|
if (err) {
|
|
printf("%s get resource [%d] owner error: %d\n",
|
|
__func__, SC_R_M4_1_PID0, err);
|
|
return false;
|
|
}
|
|
|
|
if (sc_pm_is_partition_started(-1, m4_parts[1]))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|