mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
126 lines
2.3 KiB
ArmAsm
126 lines
2.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/arch/arm/lib/memset.S
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*
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* Copyright (C) 1995-2000 Russell King
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*
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* ASM optimised string functions
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.align 5
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.syntax unified
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
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.thumb
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.thumb_func
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#endif
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ENTRY(memset)
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ands r3, r0, #3 @ 1 unaligned?
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mov ip, r0 @ preserve r0 as return value
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bne 6f @ 1
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/*
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* we know that the pointer in ip is aligned to a word boundary.
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*/
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1: orr r1, r1, r1, lsl #8
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orr r1, r1, r1, lsl #16
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mov r3, r1
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cmp r2, #16
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blt 4f
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#if ! CALGN(1)+0
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/*
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* We need 2 extra registers for this loop - use r8 and the LR
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*/
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stmfd sp!, {r8, lr}
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mov r8, r1
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mov lr, r1
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2: subs r2, r2, #64
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stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
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stmiage ip!, {r1, r3, r8, lr}
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stmiage ip!, {r1, r3, r8, lr}
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stmiage ip!, {r1, r3, r8, lr}
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bgt 2b
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ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go.
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/*
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* No need to correct the count; we're only testing bits from now on
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*/
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tst r2, #32
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stmiane ip!, {r1, r3, r8, lr}
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stmiane ip!, {r1, r3, r8, lr}
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tst r2, #16
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stmiane ip!, {r1, r3, r8, lr}
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ldmfd sp!, {r8, lr}
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#else
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/*
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* This version aligns the destination pointer in order to write
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* whole cache lines at once.
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*/
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stmfd sp!, {r4-r8, lr}
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mov r4, r1
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mov r5, r1
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mov r6, r1
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mov r7, r1
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mov r8, r1
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mov lr, r1
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cmp r2, #96
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tstgt ip, #31
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ble 3f
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and r8, ip, #31
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rsb r8, r8, #32
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sub r2, r2, r8
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movs r8, r8, lsl #(32 - 4)
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stmiacs ip!, {r4, r5, r6, r7}
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stmiami ip!, {r4, r5}
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tst r8, #(1 << 30)
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mov r8, r1
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strne r1, [ip], #4
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3: subs r2, r2, #64
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stmiage ip!, {r1, r3-r8, lr}
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stmiage ip!, {r1, r3-r8, lr}
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bgt 3b
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ldmfdeq sp!, {r4-r8, pc}
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tst r2, #32
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stmiane ip!, {r1, r3-r8, lr}
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tst r2, #16
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stmiane ip!, {r4-r7}
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ldmfd sp!, {r4-r8, lr}
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#endif
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4: tst r2, #8
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stmiane ip!, {r1, r3}
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tst r2, #4
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strne r1, [ip], #4
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/*
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* When we get here, we've got less than 4 bytes to zero. We
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* may have an unaligned pointer as well.
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*/
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5: tst r2, #2
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strbne r1, [ip], #1
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strbne r1, [ip], #1
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tst r2, #1
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strbne r1, [ip], #1
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ret lr
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6: subs r2, r2, #4 @ 1 do we have enough
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blt 5b @ 1 bytes to align with?
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cmp r3, #2 @ 1
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strblt r1, [ip], #1 @ 1
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strble r1, [ip], #1 @ 1
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strb r1, [ip], #1 @ 1
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add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
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b 1b
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ENDPROC(memset)
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