mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
210 lines
9.2 KiB
C
210 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
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*
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* This program is used to generate definitions needed by
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* assembly language modules.
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*
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* We use the technique used in the OSF Mach kernel code:
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* generate asm statements containing #defines,
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* compile this file to assembler, and then extract the
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* #defines from the assembly-language output.
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*/
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#include <common.h>
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#include <linux/kbuild.h>
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#include <linux/arm-smccc.h>
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#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
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|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
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#include <asm/arch/imx-regs.h>
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#endif
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int main(void)
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{
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/*
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* TODO : Check if each entry in this file is really necessary.
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* - struct esdramc_regs
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* - struct max_regs
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* - struct aips_regs
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* - struct aipi_regs
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* - struct clkctl
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* - struct dpll
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* are used only for generating asm-offsets.h.
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* It means their offset addresses are referenced only from assembly
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* code. Is it better to define the macros directly in headers?
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*/
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#if defined(CONFIG_MX25)
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/* Clock Control Module */
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DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
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DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
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DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
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DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
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DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
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DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
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/* Enhanced SDRAM Controller */
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DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
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DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
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DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
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/* Multi-Layer AHB Crossbar Switch */
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DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
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DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
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DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
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DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
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DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
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DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
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DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
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DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
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DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
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DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
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DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
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DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
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DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
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DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
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DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
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/* AHB <-> IP-Bus Interface */
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DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
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DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
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#endif
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#if defined(CONFIG_MX27)
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DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
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DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
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DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
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DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
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DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
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DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
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DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
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DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
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DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
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DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
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DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
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DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
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DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
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DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
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DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
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DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
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DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
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offsetof(struct system_control_regs, gpcr));
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DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
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offsetof(struct system_control_regs, fmcr));
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#endif
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#if defined(CONFIG_MX35)
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/* Round up to make sure size gives nice stack alignment */
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DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
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DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
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DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
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DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
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DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
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DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
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DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
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DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
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DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
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DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
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DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
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DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
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DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
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DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
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DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
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/* Multi-Layer AHB Crossbar Switch */
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DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
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DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
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DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
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DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
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DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
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DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
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DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
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DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
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DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
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DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
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DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
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DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
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DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
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DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
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DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
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DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
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/* AHB <-> IP-Bus Interface */
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DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
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DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
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DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
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DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
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DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
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DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
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DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
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DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
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DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
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DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
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DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
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#endif
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
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/* Round up to make sure size gives nice stack alignment */
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DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
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DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
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DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
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DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
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DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
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DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
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DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
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DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
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DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
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DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
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DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
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DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
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DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
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DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
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DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
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DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
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DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
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DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
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DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
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DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
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DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
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DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
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DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
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DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
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DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
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DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
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DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
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DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
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DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
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DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
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DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
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DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
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DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
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DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
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#if defined(CONFIG_MX53)
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DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
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#endif
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/* DPLL */
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DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
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DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
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DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
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DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
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DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
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DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
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DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
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DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
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#endif
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#ifdef CONFIG_ARM_SMCCC
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DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
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DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
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DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
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DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
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#endif
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return 0;
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}
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