mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _WARM_BOOT_H_
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#define _WARM_BOOT_H_
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#define STRAP_OPT_A_RAM_CODE_SHIFT 4
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#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
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/* Defines the supported operating modes */
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enum fuse_operating_mode {
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MODE_PRODUCTION = 3,
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MODE_UNDEFINED,
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};
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/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
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enum {
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HASH_LENGTH = 4
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};
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/* Defines the storage for a hash value (128 bits) */
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struct hash {
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u32 hash[HASH_LENGTH];
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};
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/*
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* Defines the code header information for the boot rom.
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*
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* The code immediately follows the code header.
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*
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* Note that the code header needs to be 16 bytes aligned to preserve
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* the alignment of relevant data for hash and decryption computations without
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* requiring extra copies to temporary memory areas.
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*/
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struct wb_header {
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u32 length_insecure; /* length of the code header */
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u32 reserved[3];
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struct hash hash; /* hash of header+code, starts next field*/
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struct hash random_aes_block; /* a data block to aid security. */
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u32 length_secure; /* length of the code header */
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u32 destination; /* destination address to put the wb code */
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u32 entry_point; /* execution address of the wb code */
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u32 code_length; /* length of the code */
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};
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/*
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* The warm boot code needs direct access to these registers since it runs in
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* SRAM and cannot call other U-Boot code.
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*/
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union osc_ctrl_reg {
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struct {
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u32 xoe:1;
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u32 xobp:1;
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u32 reserved0:2;
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u32 xofs:6;
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u32 reserved1:2;
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u32 xods:5;
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u32 reserved2:3;
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u32 oscfi_spare:8;
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u32 pll_ref_div:2;
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u32 osc_freq:2;
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};
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u32 word;
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};
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union pllx_base_reg {
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struct {
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u32 divm:5;
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u32 reserved0:3;
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u32 divn:10;
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u32 reserved1:2;
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u32 divp:3;
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u32 reserved2:4;
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u32 lock:1;
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u32 reserved3:1;
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u32 ref_dis:1;
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u32 enable:1;
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u32 bypass:1;
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};
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u32 word;
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};
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union pllx_misc_reg {
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struct {
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u32 vcocon:4;
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u32 lfcon:4;
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u32 cpcon:4;
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u32 lock_sel:6;
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u32 reserved0:1;
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u32 lock_enable:1;
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u32 reserved1:1;
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u32 dccon:1;
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u32 pts:2;
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u32 reserved2:6;
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u32 out1_div_byp:1;
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u32 out1_inv_clk:1;
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};
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u32 word;
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};
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/*
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* TODO: This register is not documented in the TRM yet. We could move this
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* into the EMC and give it a proper interface, but not while it is
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* undocumented.
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*/
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union scratch3_reg {
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struct {
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u32 pllx_base_divm:5;
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u32 pllx_base_divn:10;
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u32 pllx_base_divp:3;
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u32 pllx_misc_lfcon:4;
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u32 pllx_misc_cpcon:4;
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};
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u32 word;
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};
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/**
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* Save warmboot memory settings for a later resume
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*
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* @return 0 if ok, -1 on error
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*/
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int warmboot_save_sdram_params(void);
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int warmboot_prepare_code(u32 seg_address, u32 seg_length);
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int sign_data_block(u8 *source, u32 length, u8 *signature);
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void wb_start(void); /* Start of WB assembly code */
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void wb_end(void); /* End of WB assembly code */
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#endif
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