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https://github.com/brain-hackers/u-boot-brain
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39edfaa758
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_PX30_H
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#define _ASM_ARCH_SDRAM_PX30_H
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#include <asm/arch-rockchip/sdram_common.h>
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#include <asm/arch-rockchip/sdram_msch.h>
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#include <asm/arch-rockchip/sdram_pctl_px30.h>
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#include <asm/arch-rockchip/sdram_phy_px30.h>
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#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
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#define SR_IDLE 93
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#define PD_IDLE 13
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/* PMUGRF */
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#define PMUGRF_OS_REG0 (0x200)
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#define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4)
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/* DDR GRF */
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#define DDR_GRF_CON(n) (0 + (n) * 4)
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#define DDR_GRF_STATUS_BASE (0X100)
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#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
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#define DDR_GRF_LP_CON (0x20)
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#define SPLIT_MODE_32_L16_VALID (0)
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#define SPLIT_MODE_32_H16_VALID (1)
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#define SPLIT_MODE_16_L8_VALID (2)
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#define SPLIT_MODE_16_H8_VALID (3)
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#define DDR_GRF_SPLIT_CON (0x8)
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#define SPLIT_MODE_MASK (0x3)
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#define SPLIT_MODE_OFFSET (9)
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#define SPLIT_BYPASS_MASK (1)
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#define SPLIT_BYPASS_OFFSET (8)
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#define SPLIT_SIZE_MASK (0xff)
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#define SPLIT_SIZE_OFFSET (0)
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/* CRU define */
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/* CRU_PLL_CON0 */
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#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
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#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
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#define FBDIV(n) ((0xFFF << 16) | (n))
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/* CRU_PLL_CON1 */
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#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
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#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
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#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
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#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
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#define LOCK(n) (((n) >> 10) & 0x1)
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#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
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#define REFDIV(n) ((0x3F << 16) | (n))
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/* CRU_MODE */
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#define CLOCK_FROM_XIN_OSC (0)
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#define CLOCK_FROM_PLL (1)
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#define CLOCK_FROM_RTC_32K (2)
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#define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4))
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/* CRU_SOFTRESET_CON1 */
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#define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6))
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#define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5))
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#define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4))
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/* CRU_SOFTRESET_CON2 */
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#define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2))
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#define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0))
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/* CRU register */
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#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
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#define CRU_MODE (0xa0)
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#define CRU_GLB_CNT_TH (0xb0)
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#define CRU_CLKSEL_CON_BASE 0x100
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
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#define CRU_CLKGATE_CON_BASE 0x200
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#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
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#define CRU_CLKSFTRST_CON_BASE 0x300
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#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
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struct px30_ddr_grf_regs {
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u32 ddr_grf_con[4];
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u32 reserved1[(0x20 - 0x10) / 4];
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u32 ddr_grf_lp_con;
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u32 reserved2[(0x100 - 0x24) / 4];
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u32 ddr_grf_status[11];
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};
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struct msch_regs {
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u32 coreid;
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u32 revisionid;
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u32 deviceconf;
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u32 devicesize;
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u32 ddrtiminga0;
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u32 ddrtimingb0;
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u32 ddrtimingc0;
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u32 devtodev0;
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u32 reserved1[(0x110 - 0x20) / 4];
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u32 ddrmode;
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u32 ddr4timing;
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u32 reserved2[(0x1000 - 0x118) / 4];
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u32 agingx0;
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u32 reserved3[(0x1040 - 0x1004) / 4];
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u32 aging0;
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u32 aging1;
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u32 aging2;
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u32 aging3;
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};
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struct sdram_msch_timings {
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union noc_ddrtiminga0 ddrtiminga0;
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union noc_ddrtimingb0 ddrtimingb0;
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union noc_ddrtimingc0 ddrtimingc0;
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union noc_devtodev0 devtodev0;
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union noc_ddrmode ddrmode;
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union noc_ddr4timing ddr4timing;
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u32 agingx0;
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};
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struct px30_sdram_channel {
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struct sdram_cap_info cap_info;
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struct sdram_msch_timings noc_timings;
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};
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struct px30_sdram_params {
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struct px30_sdram_channel ch;
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struct sdram_base_params base;
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struct ddr_pctl_regs pctl_regs;
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struct ddr_phy_regs phy_regs;
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struct ddr_phy_skew *skew;
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};
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int sdram_init(void);
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#endif
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