176 lines
3.8 KiB
C
176 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#ifndef _ASM_ARCH_CLOCK_H
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#define _ASM_ARCH_CLOCK_H
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struct udevice;
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/* define pll mode */
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#define RKCLK_PLL_MODE_SLOW 0
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#define RKCLK_PLL_MODE_NORMAL 1
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#define RKCLK_PLL_MODE_DEEP 2
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enum {
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ROCKCHIP_SYSCON_NOC,
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ROCKCHIP_SYSCON_GRF,
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ROCKCHIP_SYSCON_SGRF,
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ROCKCHIP_SYSCON_PMU,
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ROCKCHIP_SYSCON_PMUGRF,
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ROCKCHIP_SYSCON_PMUSGRF,
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ROCKCHIP_SYSCON_CIC,
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ROCKCHIP_SYSCON_MSCH,
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};
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/* Standard Rockchip clock numbers */
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enum rk_clk_id {
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CLK_OSC,
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CLK_ARM,
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CLK_DDR,
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CLK_CODEC,
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CLK_GENERAL,
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CLK_NEW,
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CLK_COUNT,
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};
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#define PLL(_type, _id, _con, _mode, _mshift, \
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_lshift, _pflags, _rtable) \
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{ \
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.id = _id, \
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.type = _type, \
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.con_offset = _con, \
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.mode_offset = _mode, \
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.mode_shift = _mshift, \
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.lock_shift = _lshift, \
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.pll_flags = _pflags, \
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.rate_table = _rtable, \
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}
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#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
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_postdiv2, _dsmpd, _frac) \
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{ \
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.rate = _rate##U, \
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.fbdiv = _fbdiv, \
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.postdiv1 = _postdiv1, \
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.refdiv = _refdiv, \
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.postdiv2 = _postdiv2, \
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.dsmpd = _dsmpd, \
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.frac = _frac, \
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}
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struct rockchip_pll_rate_table {
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unsigned long rate;
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unsigned int nr;
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unsigned int nf;
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unsigned int no;
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unsigned int nb;
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/* for RK3036/RK3399 */
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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enum rockchip_pll_type {
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pll_rk3036,
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pll_rk3066,
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pll_rk3328,
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pll_rk3366,
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pll_rk3399,
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};
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struct rockchip_pll_clock {
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unsigned int id;
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unsigned int con_offset;
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unsigned int mode_offset;
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unsigned int mode_shift;
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unsigned int lock_shift;
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enum rockchip_pll_type type;
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unsigned int pll_flags;
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struct rockchip_pll_rate_table *rate_table;
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unsigned int mode_mask;
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};
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struct rockchip_cpu_rate_table {
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unsigned long rate;
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unsigned int aclk_div;
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unsigned int pclk_div;
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};
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int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
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void __iomem *base, ulong clk_id,
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ulong drate);
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ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
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void __iomem *base, ulong clk_id);
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const struct rockchip_cpu_rate_table *
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rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
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ulong rate);
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static inline int rk_pll_id(enum rk_clk_id clk_id)
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{
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return clk_id - 1;
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}
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struct sysreset_reg {
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unsigned int glb_srst_fst_value;
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unsigned int glb_srst_snd_value;
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};
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/**
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* clk_get_divisor() - Calculate the required clock divisior
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*
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* Given an input rate and a required output_rate, calculate the Rockchip
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* divisor needed to achieve this.
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*
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* @input_rate: Input clock rate in Hz
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* @output_rate: Output clock rate in Hz
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* @return divisor register value to use
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*/
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static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
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{
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uint clk_div;
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clk_div = input_rate / output_rate;
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clk_div = (clk_div + 1) & 0xfffe;
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return clk_div;
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}
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/**
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* rockchip_get_cru() - get a pointer to the clock/reset unit registers
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*
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* @return pointer to registers, or -ve error on error
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*/
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void *rockchip_get_cru(void);
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/**
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* rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
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*
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* @return pointer to registers, or -ve error on error
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*/
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void *rockchip_get_pmucru(void);
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struct rockchip_cru;
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struct rk3288_grf;
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void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
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int rockchip_get_clk(struct udevice **devp);
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/*
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* rockchip_reset_bind() - Bind soft reset device as child of clock device
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*
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* @pdev: clock udevice
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* @reg_offset: the first offset in cru for softreset registers
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* @reg_number: the reg numbers of softreset registers
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* @return 0 success, or error value
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*/
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int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
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#endif
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