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15b6184971
The arm64 exception handling code is quite big, mostly due to architectural alignment requirements. Each exception entry spans 32 instructions, which sounds generous, but is too small to fit all of the save/branch/restore code in there. So at the moment we use only four instructions, branching into shared save and restore routines. To not leave the space for those remaining 28 instructions wasted, let's split the save and restore routines and stuff them into the gaps. This saves about 250 bytes of code, which is helpful for those tight SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
161 lines
4.3 KiB
ArmAsm
161 lines
4.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/ptrace.h>
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#include <asm/macro.h>
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#include <linux/linkage.h>
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/*
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* AArch64 exception vectors:
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* We have four types of exceptions:
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* - synchronous: traps, data aborts, undefined instructions, ...
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* - IRQ: group 1 (normal) interrupts
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* - FIQ: group 0 or secure interrupts
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* - SError: fatal system errors
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* There are entries for all four of those for different contexts:
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* - from same exception level, when using the SP_EL0 stack pointer
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* - from same exception level, when using the SP_ELx stack pointer
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* - from lower exception level, when this is AArch64
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* - from lower exception level, when this is AArch32
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* Each of those 16 entries have space for 32 instructions, each entry must
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* be 128 byte aligned, the whole table must be 2K aligned.
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* The 32 instructions are not enough to save and restore all registers and
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* to branch to the actual handler, so we split this up:
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* Each entry saves the LR, branches to the save routine, then to the actual
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* handler, then to the restore routine. The save and restore routines are
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* each split in half and stuffed in the unused gap between the entries.
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* Also as we do not run anything in a lower exception level, we just provide
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* the first 8 entries for exceptions from the same EL.
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*/
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.align 11
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.globl vectors
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vectors:
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.align 7 /* Current EL Synchronous Thread */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_bad_sync
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b exception_exit
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/*
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* Save (most of) the GP registers to the stack frame.
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* This is the first part of the shared routine called into from all entries.
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*/
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_exception_entry:
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stp x27, x28, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x19, x20, [sp, #-16]!
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stp x17, x18, [sp, #-16]!
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stp x15, x16, [sp, #-16]!
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stp x13, x14, [sp, #-16]!
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stp x11, x12, [sp, #-16]!
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stp x9, x10, [sp, #-16]!
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stp x7, x8, [sp, #-16]!
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stp x5, x6, [sp, #-16]!
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stp x3, x4, [sp, #-16]!
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stp x1, x2, [sp, #-16]!
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b _save_el_regs /* jump to the second part */
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.align 7 /* Current EL IRQ Thread */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_bad_irq
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b exception_exit
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/*
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* Save exception specific context: ESR and ELR, for all exception levels.
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* This is the second part of the shared routine called into from all entries.
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*/
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_save_el_regs:
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/* Could be running at EL3/EL2/EL1 */
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switch_el x11, 3f, 2f, 1f
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3: mrs x1, esr_el3
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mrs x2, elr_el3
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b 0f
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2: mrs x1, esr_el2
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mrs x2, elr_el2
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b 0f
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1: mrs x1, esr_el1
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mrs x2, elr_el1
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0:
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stp x2, x0, [sp, #-16]!
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mov x0, sp
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ret
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.align 7 /* Current EL FIQ Thread */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_bad_fiq
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/* falling through to _exception_exit */
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/*
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* Restore the exception return address, for all exception levels.
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* This is the first part of the shared routine called into from all entries.
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*/
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exception_exit:
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ldp x2, x0, [sp],#16
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switch_el x11, 3f, 2f, 1f
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3: msr elr_el3, x2
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b _restore_regs
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2: msr elr_el2, x2
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b _restore_regs
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1: msr elr_el1, x2
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b _restore_regs /* jump to the second part */
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.align 7 /* Current EL Error Thread */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_bad_error
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b exception_exit
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/*
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* Restore the general purpose registers from the exception stack, then return.
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* This is the second part of the shared routine called into from all entries.
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*/
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_restore_regs:
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ldp x1, x2, [sp],#16
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ldp x3, x4, [sp],#16
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ldp x5, x6, [sp],#16
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ldp x7, x8, [sp],#16
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ldp x9, x10, [sp],#16
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ldp x11, x12, [sp],#16
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ldp x13, x14, [sp],#16
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ldp x15, x16, [sp],#16
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ldp x17, x18, [sp],#16
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ldp x19, x20, [sp],#16
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ldp x21, x22, [sp],#16
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ldp x23, x24, [sp],#16
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ldp x25, x26, [sp],#16
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ldp x27, x28, [sp],#16
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ldp x29, x30, [sp],#16
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eret
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.align 7 /* Current EL (SP_ELx) Synchronous Handler */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_sync
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b exception_exit
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.align 7 /* Current EL (SP_ELx) IRQ Handler */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_irq
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b exception_exit
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.align 7 /* Current EL (SP_ELx) FIQ Handler */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_fiq
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b exception_exit
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.align 7 /* Current EL (SP_ELx) Error Handler */
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stp x29, x30, [sp, #-16]!
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bl _exception_entry
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bl do_error
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b exception_exit
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