mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
268 lines
5.9 KiB
ArmAsm
268 lines
5.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* This file is based on sample code from ARMv8 ARM.
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/macro.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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/*
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* void __asm_dcache_level(level)
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*
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* flush or invalidate one level cache.
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*
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* x0: cache level
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* x1: 0 clean & invalidate, 1 invalidate only
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* x2~x9: clobbered
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*/
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.pushsection .text.__asm_dcache_level, "ax"
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ENTRY(__asm_dcache_level)
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lsl x12, x0, #1
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msr csselr_el1, x12 /* select cache level */
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isb /* sync change of cssidr_el1 */
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mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
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and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
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add x2, x2, #4 /* x2 <- log2(cache line size) */
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mov x3, #0x3ff
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and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
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clz w5, w3 /* bit position of #ways */
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mov x4, #0x7fff
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and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
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/* x12 <- cache level << 1 */
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/* x2 <- line length offset */
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/* x3 <- number of cache ways - 1 */
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/* x4 <- number of cache sets - 1 */
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/* x5 <- bit position of #ways */
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loop_set:
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mov x6, x3 /* x6 <- working copy of #ways */
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loop_way:
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lsl x7, x6, x5
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orr x9, x12, x7 /* map way and level to cisw value */
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lsl x7, x4, x2
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orr x9, x9, x7 /* map set number to cisw value */
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tbz w1, #0, 1f
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dc isw, x9
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b 2f
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1: dc cisw, x9 /* clean & invalidate by set/way */
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2: subs x6, x6, #1 /* decrement the way */
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b.ge loop_way
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subs x4, x4, #1 /* decrement the set */
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b.ge loop_set
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ret
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ENDPROC(__asm_dcache_level)
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.popsection
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/*
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* void __asm_flush_dcache_all(int invalidate_only)
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*
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* x0: 0 clean & invalidate, 1 invalidate only
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*
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* flush or invalidate all data cache by SET/WAY.
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*/
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.pushsection .text.__asm_dcache_all, "ax"
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ENTRY(__asm_dcache_all)
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mov x1, x0
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dsb sy
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mrs x10, clidr_el1 /* read clidr_el1 */
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lsr x11, x10, #24
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and x11, x11, #0x7 /* x11 <- loc */
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cbz x11, finished /* if loc is 0, exit */
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mov x15, lr
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mov x0, #0 /* start flush at cache level 0 */
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/* x0 <- cache level */
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/* x10 <- clidr_el1 */
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/* x11 <- loc */
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/* x15 <- return address */
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loop_level:
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lsl x12, x0, #1
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add x12, x12, x0 /* x0 <- tripled cache level */
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lsr x12, x10, x12
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and x12, x12, #7 /* x12 <- cache type */
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cmp x12, #2
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b.lt skip /* skip if no cache or icache */
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bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
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skip:
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add x0, x0, #1 /* increment cache level */
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cmp x11, x0
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b.gt loop_level
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mov x0, #0
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msr csselr_el1, x0 /* restore csselr_el1 */
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dsb sy
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isb
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mov lr, x15
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finished:
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ret
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ENDPROC(__asm_dcache_all)
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.popsection
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.pushsection .text.__asm_flush_dcache_all, "ax"
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ENTRY(__asm_flush_dcache_all)
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mov x0, #0
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b __asm_dcache_all
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ENDPROC(__asm_flush_dcache_all)
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.popsection
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.pushsection .text.__asm_invalidate_dcache_all, "ax"
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ENTRY(__asm_invalidate_dcache_all)
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mov x0, #0x1
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b __asm_dcache_all
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ENDPROC(__asm_invalidate_dcache_all)
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.popsection
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/*
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* void __asm_flush_dcache_range(start, end)
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*
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* clean & invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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.pushsection .text.__asm_flush_dcache_range, "ax"
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ENTRY(__asm_flush_dcache_range)
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mrs x3, ctr_el0
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lsr x3, x3, #16
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and x3, x3, #0xf
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc civac, x0 /* clean & invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(__asm_flush_dcache_range)
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.popsection
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/*
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* void __asm_invalidate_dcache_range(start, end)
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*
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* invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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.pushsection .text.__asm_invalidate_dcache_range, "ax"
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ENTRY(__asm_invalidate_dcache_range)
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mrs x3, ctr_el0
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ubfm x3, x3, #16, #19
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc ivac, x0 /* invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(__asm_invalidate_dcache_range)
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.popsection
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/*
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* void __asm_invalidate_icache_all(void)
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*
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* invalidate all tlb entries.
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*/
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.pushsection .text.__asm_invalidate_icache_all, "ax"
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ENTRY(__asm_invalidate_icache_all)
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ic ialluis
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isb sy
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ret
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ENDPROC(__asm_invalidate_icache_all)
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.popsection
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.pushsection .text.__asm_invalidate_l3_dcache, "ax"
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ENTRY(__asm_invalidate_l3_dcache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_invalidate_l3_dcache)
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.weak __asm_invalidate_l3_dcache
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.popsection
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.pushsection .text.__asm_flush_l3_dcache, "ax"
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ENTRY(__asm_flush_l3_dcache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_flush_l3_dcache)
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.weak __asm_flush_l3_dcache
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.popsection
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.pushsection .text.__asm_invalidate_l3_icache, "ax"
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ENTRY(__asm_invalidate_l3_icache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_invalidate_l3_icache)
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.weak __asm_invalidate_l3_icache
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.popsection
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/*
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* void __asm_switch_ttbr(ulong new_ttbr)
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*
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* Safely switches to a new page table.
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*/
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.pushsection .text.__asm_switch_ttbr, "ax"
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ENTRY(__asm_switch_ttbr)
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/* x2 = SCTLR (alive throghout the function) */
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switch_el x4, 3f, 2f, 1f
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3: mrs x2, sctlr_el3
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b 0f
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2: mrs x2, sctlr_el2
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b 0f
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1: mrs x2, sctlr_el1
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0:
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/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
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movn x1, #(CR_M | CR_C | CR_I)
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and x1, x2, x1
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switch_el x4, 3f, 2f, 1f
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3: msr sctlr_el3, x1
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b 0f
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2: msr sctlr_el2, x1
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b 0f
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1: msr sctlr_el1, x1
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0: isb
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/* This call only clobbers x30 (lr) and x9 (unused) */
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mov x3, x30
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bl __asm_invalidate_tlb_all
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/* From here on we're running safely with caches disabled */
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/* Set TTBR to our first argument */
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switch_el x4, 3f, 2f, 1f
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3: msr ttbr0_el3, x0
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b 0f
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2: msr ttbr0_el2, x0
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b 0f
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1: msr ttbr0_el1, x0
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0: isb
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/* Restore original SCTLR and thus enable caches again */
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switch_el x4, 3f, 2f, 1f
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3: msr sctlr_el3, x2
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b 0f
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2: msr sctlr_el2, x2
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b 0f
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1: msr sctlr_el1, x2
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0: isb
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ret x3
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ENDPROC(__asm_switch_ttbr)
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.popsection
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