123 lines
2.5 KiB
C
123 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/tieoff.h>
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#include <cpu_func.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_ARCH_CPU_INIT
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#error must be define the macro "CONFIG_ARCH_CPU_INIT"
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#endif
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void s_init(void)
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{
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}
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static void cpu_soc_init(void)
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{
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/*
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* NOTE> ALIVE Power Gate must enable for Alive register access.
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* must be clear wfi jump address
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*/
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writel(1, ALIVEPWRGATEREG);
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writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
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/* write 0xf0 on alive scratchpad reg for boot success check */
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writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
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/* set l2 cache tieoff */
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nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
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nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
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}
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#ifdef CONFIG_PL011_SERIAL
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static void serial_device_init(void)
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{
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char dev[10];
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int id;
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sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
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id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
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struct clk *clk = clk_get((const char *)dev);
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/* reset control: Low active ___|--- */
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nx_rstcon_setrst(id, RSTCON_ASSERT);
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udelay(10);
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nx_rstcon_setrst(id, RSTCON_NEGATE);
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udelay(10);
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/* set clock */
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clk_disable(clk);
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clk_set_rate(clk, CONFIG_PL011_CLOCK);
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clk_enable(clk);
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}
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#endif
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int arch_cpu_init(void)
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{
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flush_dcache_all();
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cpu_soc_init();
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clk_init();
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if (IS_ENABLED(CONFIG_PL011_SERIAL))
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serial_device_init();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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return 0;
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}
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#endif
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void reset_cpu(ulong ignored)
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{
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void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
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const u32 sw_rst_enb_bitpos = 3;
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const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
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const u32 sw_rst_bitpos = 12;
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const u32 sw_rst_mask = 1 << sw_rst_bitpos;
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int pwrcont = 0x224;
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int pwrmode = 0x228;
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u32 read_value;
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read_value = readl((void *)(clkpwr_reg + pwrcont));
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read_value &= ~sw_rst_enb_mask;
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read_value |= 1 << sw_rst_enb_bitpos;
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writel(read_value, (void *)(clkpwr_reg + pwrcont));
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writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
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}
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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