mirror of
https://github.com/brain-hackers/u-boot-brain
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6d09581f78
The _main call is not supposed to return at all: don't link the branch. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Stefan Roese <sr@denx.de>
66 lines
1.7 KiB
ArmAsm
66 lines
1.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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*/
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#include <config.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* The BootROM already initialized its own stack in the [0-0xb00] reserved
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* range of the SRAM. The SPL (in _main) will update the stack pointer to
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* its own SRAM area (right before the gd section).
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*
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*************************************************************************
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*/
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.globl reset
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.globl back_to_bootrom
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reset:
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/*
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* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
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* UART boot, USB boot): save registers in BootROM's stack and then the
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* BootROM's stack pointer in the SPL's data section.
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*/
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push {r0-r12,lr}
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ldr r0, =bootrom_stash_sp
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str sp, [r0]
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/*
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* Flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
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/*
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* Enable instruction cache
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*/
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Go setup Memory and board specific bits prior to relocation.
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* This call is not supposed to return.
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*/
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b _main /* _main will call board_init_f */
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back_to_bootrom:
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pop {r0-r12,pc}
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