mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
2ff50f5fa4
With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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enum pei_boot_mode_t {
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PEI_BOOT_NONE = 0,
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PEI_BOOT_SOFT_RESET,
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PEI_BOOT_RESUME,
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};
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struct dimm_info {
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uint32_t dimm_size;
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uint16_t ddr_type;
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uint16_t ddr_frequency;
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uint8_t rank_per_dimm;
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uint8_t channel_num;
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uint8_t dimm_num;
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uint8_t bank_locator;
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/* The 5th byte is '\0' for the end of string */
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uint8_t serial[5];
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/* The 19th byte is '\0' for the end of string */
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uint8_t module_part_number[19];
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uint16_t mod_id;
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uint8_t mod_type;
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uint8_t bus_width;
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} __packed;
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struct pei_memory_info {
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uint8_t dimm_cnt;
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/* Maximum num of dimm is 8 */
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struct dimm_info dimm[8];
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} __packed;
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struct memory_area {
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uint64_t start;
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uint64_t size;
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};
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struct memory_info {
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int num_areas;
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uint64_t total_memory;
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uint64_t total_32bit_memory;
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struct memory_area area[CONFIG_NR_DRAM_BANKS];
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};
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#define MAX_MTRR_REQUESTS 8
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/**
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* A request for a memory region to be set up in a particular way. These
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* requests are processed before board_init_r() is called. They are generally
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* optional and can be ignored with some performance impact.
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*/
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struct mtrr_request {
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int type; /* MTRR_TYPE_... */
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uint64_t start;
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uint64_t size;
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};
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/* Architecture-specific global data */
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struct arch_global_data {
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u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
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struct global_data *gd_addr; /* Location of Global Data */
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uint8_t x86; /* CPU family */
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uint8_t x86_vendor; /* CPU vendor */
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uint8_t x86_model;
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uint8_t x86_mask;
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uint32_t x86_device;
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uint64_t tsc_base; /* Initial value returned by rdtsc() */
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unsigned long clock_rate; /* Clock rate of timer in Hz */
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void *new_fdt; /* Relocated FDT */
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uint32_t bist; /* Built-in self test value */
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enum pei_boot_mode_t pei_boot_mode;
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const struct pch_gpio_map *gpio_map; /* board GPIO map */
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struct memory_info meminfo; /* Memory information */
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struct pei_memory_info pei_meminfo; /* PEI memory information */
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#ifdef CONFIG_HAVE_FSP
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void *hob_list; /* FSP HOB list */
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#endif
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struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
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int mtrr_req_count;
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int has_mtrr;
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/* MRC training data to save for the next boot */
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char *mrc_output;
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unsigned int mrc_output_len;
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ulong table; /* Table pointer from previous loader */
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int turbo_state; /* Current turbo state */
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struct irq_routing_table *pirq_routing_table;
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#ifdef CONFIG_SEABIOS
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u32 high_table_ptr;
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u32 high_table_limit;
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#endif
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#ifdef CONFIG_HAVE_ACPI_RESUME
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int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */
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ulong backup_mem; /* Backup memory address for S3 */
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#endif
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};
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#endif
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#include <asm-generic/global_data.h>
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#ifndef __ASSEMBLY__
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# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
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/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
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#define gd global_data_ptr
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#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
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# else
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static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
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{
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gd_t *gd_ptr;
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#if CONFIG_IS_ENABLED(X86_64)
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asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
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#else
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asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
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#endif
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return gd_ptr;
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}
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#define gd get_fs_gd_ptr()
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#define DECLARE_GLOBAL_DATA_PTR
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# endif
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#endif
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/*
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* Our private Global Data Flags
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*/
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#define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */
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#define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */
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#endif /* __ASM_GBL_DATA_H */
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