mirror of
https://github.com/brain-hackers/u-boot-brain
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3ff2f001c2
It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_ARCH_MISC_INIT
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#define CONFIG_SMSC_LPC47M
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x80000000
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#define CONFIG_PCI_PREF_BUS 0xc0000000
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#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
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#define CONFIG_PCI_PREF_SIZE 0x20000000
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#define CONFIG_PCI_IO_BUS 0x2000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xe000
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
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"stdout=serial,vga\0" \
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"stderr=serial,vga\0"
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#define CONFIG_SCSI_DEV_LIST \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
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#define CONFIG_SPI_FLASH_SST
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#define CONFIG_MMC
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#define CONFIG_SDHCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC_SDMA
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#define CONFIG_CMD_MMC
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/* Topcliff Gigabit Ethernet */
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#define CONFIG_PCH_GBE
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#define CONFIG_PHYLIB
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/* TunnelCreek IGD support */
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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/* Environment configuration */
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_OFFSET 0
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#endif /* __CONFIG_H */
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