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https://github.com/brain-hackers/u-boot-brain
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476f7090bf
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII * configures the RGMII pins (in GPIOC) when requested via pinctrl X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_PERIPH_H
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#define _ASM_ARCH_PERIPH_H
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/*
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* The peripherals supported by the hardware. This is used to specify clocks
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* and pinctrl settings. Some SoCs will not support all of these, but it
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* provides a common reference for common drivers to use.
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*/
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enum periph_id {
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PERIPH_ID_PWM0,
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PERIPH_ID_PWM1,
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PERIPH_ID_PWM2,
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PERIPH_ID_PWM3,
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PERIPH_ID_PWM4,
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PERIPH_ID_I2C0,
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PERIPH_ID_I2C1,
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PERIPH_ID_I2C2,
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PERIPH_ID_I2C3,
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PERIPH_ID_I2C4,
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PERIPH_ID_I2C5,
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PERIPH_ID_SPI0,
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PERIPH_ID_SPI1,
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PERIPH_ID_SPI2,
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PERIPH_ID_UART0,
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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PERIPH_ID_UART3,
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PERIPH_ID_UART4,
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PERIPH_ID_LCDC0,
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PERIPH_ID_LCDC1,
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PERIPH_ID_SDMMC0,
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PERIPH_ID_SDMMC1,
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PERIPH_ID_SDMMC2,
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PERIPH_ID_HDMI,
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PERIPH_ID_GMAC,
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PERIPH_ID_COUNT,
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/* Some aliases */
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PERIPH_ID_EMMC = PERIPH_ID_SDMMC0,
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PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1,
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PERIPH_ID_UART_BT = PERIPH_ID_UART0,
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PERIPH_ID_UART_BB = PERIPH_ID_UART1,
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PERIPH_ID_UART_DBG = PERIPH_ID_UART2,
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PERIPH_ID_UART_GPS = PERIPH_ID_UART3,
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PERIPH_ID_UART_EXP = PERIPH_ID_UART4,
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};
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#endif
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