mirror of
https://github.com/brain-hackers/u-boot-brain
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3fd673cf36
The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0: 64M Non-cacheable, guarded
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* 0xfc000000 56M unused
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* 0xff800000 8M boot FLASH
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* .... or ....
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* 0xfc000000 64M user flash
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*
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 512M PCI1 MEM
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* 0xa0000000 512M PCIe MEM
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1G, 1),
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/*
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* TLB 2: 64M Non-cacheable, guarded
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* 0xe0000000 1M CCSRBAR
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* 0xe2000000 8M PCI1 IO
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* 0xe2800000 8M PCIe IO
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 3: 64M Cacheable, non-guarded
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* 0xf0000000 64M LBC SDRAM First half
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 3, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 4: 64M Cacheable, non-guarded
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* 0xf4000000 64M LBC SDRAM Second half
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
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CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 4, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 5: 16M Cacheable, non-guarded
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* 0xf8000000 1M 7-segment LED display
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* 0xf8100000 1M User switches
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* 0xf8300000 1M Board revision
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* 0xf8b00000 1M EEPROM
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_16M, 1),
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xec000000 64M 64MB user FLASH
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_64M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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