mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 20:09:43 +09:00
3fcdd4a5f8
The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
437 lines
14 KiB
C
437 lines
14 KiB
C
/*
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*
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* HW data initialization for OMAP5
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clocks.h>
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#include <asm/omap_gpio.h>
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#include <asm/io.h>
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struct prcm_regs const **prcm =
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(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
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struct dplls const **dplls_data =
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(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
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struct vcores_data const **omap_vcores =
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(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
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static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
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{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
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{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
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{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
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{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params
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core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
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{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
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{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
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{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
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};
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static const struct dpll_params
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core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
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{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
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{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
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{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
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{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
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{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
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{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
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{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
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{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
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{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1, -1, -1
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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struct dplls omap5_dplls_es1 = {
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.mpu = mpu_dpll_params_800mhz,
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.core = core_dpll_params_2128mhz_ddr532,
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.per = per_dpll_params_768mhz,
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.iva = iva_dpll_params_2330mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz
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};
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struct pmic_data palmas = {
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.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
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.step = 10000, /* 10 mV represented in uV */
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/*
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* Offset codes 1-6 all give the base voltage in Palmas
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* Offset code 0 switches OFF the SMPS
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*/
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.start_code = 6,
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};
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struct vcores_data omap5430_volts = {
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.mpu.value = VDD_MPU,
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.mpu.addr = SMPS_REG_ADDR_12_MPU,
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.mpu.pmic = &palmas,
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.core.value = VDD_CORE,
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.core.addr = SMPS_REG_ADDR_8_CORE,
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.core.pmic = &palmas,
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.mm.value = VDD_MM,
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.mm.addr = SMPS_REG_ADDR_45_IVA,
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.mm.pmic = &palmas,
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};
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struct vcores_data omap5432_volts = {
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.mpu.value = VDD_MPU_5432,
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.mpu.addr = SMPS_REG_ADDR_12_MPU,
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.mpu.pmic = &palmas,
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.core.value = VDD_CORE_5432,
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.core.addr = SMPS_REG_ADDR_8_CORE,
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.core.pmic = &palmas,
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.mm.value = VDD_MM_5432,
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.mm.addr = SMPS_REG_ADDR_45_IVA,
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.mm.pmic = &palmas,
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};
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/*
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* Enable essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_basic_clocks(void)
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{
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u32 const clk_domains_essential[] = {
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(*prcm)->cm_l4per_clkstctrl,
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(*prcm)->cm_l3init_clkstctrl,
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(*prcm)->cm_memif_clkstctrl,
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(*prcm)->cm_l4cfg_clkstctrl,
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0
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};
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u32 const clk_modules_hw_auto_essential[] = {
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(*prcm)->cm_l3_2_gpmc_clkctrl,
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(*prcm)->cm_memif_emif_1_clkctrl,
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(*prcm)->cm_memif_emif_2_clkctrl,
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(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
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(*prcm)->cm_wkup_gpio1_clkctrl,
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(*prcm)->cm_l4per_gpio2_clkctrl,
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(*prcm)->cm_l4per_gpio3_clkctrl,
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(*prcm)->cm_l4per_gpio4_clkctrl,
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(*prcm)->cm_l4per_gpio5_clkctrl,
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(*prcm)->cm_l4per_gpio6_clkctrl,
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0
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};
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u32 const clk_modules_explicit_en_essential[] = {
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(*prcm)->cm_wkup_gptimer1_clkctrl,
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(*prcm)->cm_l3init_hsmmc1_clkctrl,
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(*prcm)->cm_l3init_hsmmc2_clkctrl,
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(*prcm)->cm_l4per_gptimer2_clkctrl,
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(*prcm)->cm_wkup_wdtimer2_clkctrl,
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(*prcm)->cm_l4per_uart3_clkctrl,
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(*prcm)->cm_l4per_i2c1_clkctrl,
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0
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};
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/* Enable optional additional functional clock for GPIO4 */
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setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
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GPIO4_CLKCTRL_OPTFCLKEN_MASK);
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/* Enable 96 MHz clock for MMC1 & MMC2 */
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setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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/* Set the correct clock dividers for mmc */
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setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
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setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
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/* Select 32KHz clock as the source of GPTIMER1 */
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setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
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GPTIMER1_CLKCTRL_CLKSEL_MASK);
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do_enable_clocks(clk_domains_essential,
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clk_modules_hw_auto_essential,
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clk_modules_explicit_en_essential,
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1);
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/* Select 384Mhz for GPU as its the POR for ES1.0 */
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setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
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CLKSEL_GPU_HYD_GCLK_MASK);
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setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
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CLKSEL_GPU_CORE_GCLK_MASK);
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/* Enable SCRM OPT clocks for PER and CORE dpll */
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setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
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OPTFCLKEN_SCRM_PER_MASK);
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setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
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OPTFCLKEN_SCRM_CORE_MASK);
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}
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void enable_basic_uboot_clocks(void)
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{
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u32 const clk_domains_essential[] = {
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0
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};
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u32 const clk_modules_hw_auto_essential[] = {
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0
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};
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u32 const clk_modules_explicit_en_essential[] = {
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(*prcm)->cm_l4per_mcspi1_clkctrl,
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(*prcm)->cm_l4per_i2c2_clkctrl,
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(*prcm)->cm_l4per_i2c3_clkctrl,
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(*prcm)->cm_l4per_i2c4_clkctrl,
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(*prcm)->cm_l3init_hsusbtll_clkctrl,
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(*prcm)->cm_l3init_hsusbhost_clkctrl,
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(*prcm)->cm_l3init_fsusb_clkctrl,
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0
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};
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do_enable_clocks(clk_domains_essential,
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clk_modules_hw_auto_essential,
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clk_modules_explicit_en_essential,
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1);
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}
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/*
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* Enable non-essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_non_essential_clocks(void)
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{
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u32 const clk_domains_non_essential[] = {
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(*prcm)->cm_mpu_m3_clkstctrl,
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(*prcm)->cm_ivahd_clkstctrl,
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(*prcm)->cm_dsp_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sgx_clkstctrl,
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(*prcm)->cm1_abe_clkstctrl,
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(*prcm)->cm_c2c_clkstctrl,
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(*prcm)->cm_cam_clkstctrl,
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(*prcm)->cm_dss_clkstctrl,
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(*prcm)->cm_sdma_clkstctrl,
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0
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};
|
|
|
|
u32 const clk_modules_hw_auto_non_essential[] = {
|
|
(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
|
|
(*prcm)->cm_ivahd_ivahd_clkctrl,
|
|
(*prcm)->cm_ivahd_sl2_clkctrl,
|
|
(*prcm)->cm_dsp_dsp_clkctrl,
|
|
(*prcm)->cm_l3instr_l3_3_clkctrl,
|
|
(*prcm)->cm_l3instr_l3_instr_clkctrl,
|
|
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
|
|
(*prcm)->cm_l3init_hsi_clkctrl,
|
|
(*prcm)->cm_l4per_hdq1w_clkctrl,
|
|
0
|
|
};
|
|
|
|
u32 const clk_modules_explicit_en_non_essential[] = {
|
|
(*prcm)->cm1_abe_aess_clkctrl,
|
|
(*prcm)->cm1_abe_pdm_clkctrl,
|
|
(*prcm)->cm1_abe_dmic_clkctrl,
|
|
(*prcm)->cm1_abe_mcasp_clkctrl,
|
|
(*prcm)->cm1_abe_mcbsp1_clkctrl,
|
|
(*prcm)->cm1_abe_mcbsp2_clkctrl,
|
|
(*prcm)->cm1_abe_mcbsp3_clkctrl,
|
|
(*prcm)->cm1_abe_slimbus_clkctrl,
|
|
(*prcm)->cm1_abe_timer5_clkctrl,
|
|
(*prcm)->cm1_abe_timer6_clkctrl,
|
|
(*prcm)->cm1_abe_timer7_clkctrl,
|
|
(*prcm)->cm1_abe_timer8_clkctrl,
|
|
(*prcm)->cm1_abe_wdt3_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer9_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer10_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer11_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer3_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer4_clkctrl,
|
|
(*prcm)->cm_l4per_mcspi2_clkctrl,
|
|
(*prcm)->cm_l4per_mcspi3_clkctrl,
|
|
(*prcm)->cm_l4per_mcspi4_clkctrl,
|
|
(*prcm)->cm_l4per_mmcsd3_clkctrl,
|
|
(*prcm)->cm_l4per_mmcsd4_clkctrl,
|
|
(*prcm)->cm_l4per_mmcsd5_clkctrl,
|
|
(*prcm)->cm_l4per_uart1_clkctrl,
|
|
(*prcm)->cm_l4per_uart2_clkctrl,
|
|
(*prcm)->cm_l4per_uart4_clkctrl,
|
|
(*prcm)->cm_wkup_keyboard_clkctrl,
|
|
(*prcm)->cm_wkup_wdtimer2_clkctrl,
|
|
(*prcm)->cm_cam_iss_clkctrl,
|
|
(*prcm)->cm_cam_fdif_clkctrl,
|
|
(*prcm)->cm_dss_dss_clkctrl,
|
|
(*prcm)->cm_sgx_sgx_clkctrl,
|
|
0
|
|
};
|
|
|
|
/* Enable optional functional clock for ISS */
|
|
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
/* Enable all optional functional clocks of DSS */
|
|
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
do_enable_clocks(clk_domains_non_essential,
|
|
clk_modules_hw_auto_non_essential,
|
|
clk_modules_explicit_en_non_essential,
|
|
0);
|
|
|
|
/* Put camera module in no sleep mode */
|
|
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
}
|
|
|
|
void hw_data_init(void)
|
|
{
|
|
u32 omap_rev = omap_revision();
|
|
|
|
switch (omap_rev) {
|
|
|
|
case OMAP5430_ES1_0:
|
|
*prcm = &omap5_es1_prcm;
|
|
*dplls_data = &omap5_dplls_es1;
|
|
*omap_vcores = &omap5430_volts;
|
|
break;
|
|
|
|
case OMAP5432_ES1_0:
|
|
*prcm = &omap5_es1_prcm;
|
|
*dplls_data = &omap5_dplls_es1;
|
|
*omap_vcores = &omap5432_volts;
|
|
break;
|
|
|
|
default:
|
|
printf("\n INVALID OMAP REVISION ");
|
|
}
|
|
}
|