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https://github.com/brain-hackers/u-boot-brain
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f861f51c46
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
18 lines
541 B
Makefile
18 lines
541 B
Makefile
#
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# (C) Copyright 2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
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obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
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ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
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obj-y += imx_watchdog.o
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endif
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obj-$(CONFIG_S5P) += s5p_wdt.o
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obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
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obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
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obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
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obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
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