mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-03 01:50:43 +09:00
3f701cc50a
To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SECURE_BOOT_H
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#define __FSL_SECURE_BOOT_H
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#ifdef CONFIG_SECURE_BOOT
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#ifndef CONFIG_FIT_SIGNATURE
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#define CONFIG_CHAIN_OF_TRUST
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#endif
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_CMD_BLOB
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#define CONFIG_CMD_HASH
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#define CONFIG_FSL_SEC_MON
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#define CONFIG_SHA_HW_ACCEL
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#define CONFIG_SHA_PROG_HW_ACCEL
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#define CONFIG_RSA_FREESCALE_EXP
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#ifndef CONFIG_FSL_CAAM
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#define CONFIG_FSL_CAAM
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#endif
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#define CONFIG_KEY_REVOCATION
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#ifndef CONFIG_SYS_RAMBOOT
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/* The key used for verification of next level images
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* is picked up from an Extension Table which has
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* been verified by the ISBC (Internal Secure boot Code)
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* in boot ROM of the SoC.
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* The feature is only applicable in case of NOR boot and is
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* not applicable in case of RAMBOOT (NAND, SD, SPI).
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*/
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#ifndef CONFIG_ESBC_HDR_LS
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/* Current Key EXT feature not available in LS ESBC Header */
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#define CONFIG_FSL_ISBC_KEY_EXT
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#endif
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#endif
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#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
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defined(CONFIG_LS2085A)
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/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
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* Similiarly for LS2080 and LS2085
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*/
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#define CONFIG_ESBC_ADDR_64BIT
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#endif
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#define CONFIG_EXTRA_ENV \
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"setenv fdt_high 0xcfffffff;" \
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"setenv initrd_high 0xcfffffff;" \
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"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
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/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
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* Non-XIP Memory (Nand/SD)*/
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
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defined(CONFIG_LS2085A)
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#define CONFIG_BOOTSCRIPT_COPY_RAM
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#endif
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/* The address needs to be modified according to NOR and DDR memory map */
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
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#define CONFIG_BS_ADDR_FLASH 0x583900000
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#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
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#define CONFIG_BS_ADDR_RAM 0xa3900000
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#else
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#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
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#define CONFIG_BS_ADDR_FLASH 0x60060000
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#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
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#define CONFIG_BS_ADDR_RAM 0xa0060000
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#endif
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#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
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#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
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#define CONFIG_BS_HDR_SIZE 0x00002000
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#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
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#define CONFIG_BS_SIZE 0x00001000
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#else
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#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
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/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
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#endif
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#include <config_fsl_chain_trust.h>
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#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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#endif
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