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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
/*
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* Copyright 2007-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/fsl_serdes.h>
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_PCIE4
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static struct pci_controller pcie4_hose;
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#endif
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[4];
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u32 devdisr;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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debug (" pci_init_board: devdisr=%x\n", devdisr);
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#ifdef CONFIG_PCIE1
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pcie_configured = is_serdes_configured(PCIE1);
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if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
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set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_1);
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set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_1);
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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pcie_configured = is_serdes_configured(PCIE2);
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if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
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set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_2);
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set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_2);
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf("PCIE2: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCIE3
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pcie_configured = is_serdes_configured(PCIE3);
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if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
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set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_3);
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set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_3);
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf("PCIE3: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
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#endif
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#ifdef CONFIG_PCIE4
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pcie_configured = is_serdes_configured(PCIE4);
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if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
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set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_4);
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set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_4);
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SET_STD_PCIE_INFO(pci_info[num], 4);
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pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
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printf("PCIE4: connected to as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie4_hose, first_free_busno);
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} else {
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printf("PCIE4: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
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#endif
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}
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void pci_of_setup(void *blob, bd_t *bd)
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{
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FT_FSL_PCI_SETUP;
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}
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