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https://github.com/brain-hackers/u-boot-brain
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![Troy Kisky](/assets/img/avatar_default.png)
This will be used by usb_lowlevel_init so it will no longer be used by only board specific functions. Move definition of enum usb_init_type higher in file so that it will be available for usb_low_level_init. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
136 lines
2.6 KiB
C
136 lines
2.6 KiB
C
/*
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* ICP DAS LP-8x4x Support
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* adapted from Voipac PXA270 Support by
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* Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/regs-mmc.h>
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#include <asm/arch/pxa.h>
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#include <netdev.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bis)
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{
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pxa_mmc_register(0);
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return 0;
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}
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#endif
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#ifdef CONFIG_CMD_USB
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int board_usb_init(int index, enum usb_init_type init)
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{
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writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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continue; /* required by checkpath.pl */
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
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writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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/* enable port 2 */
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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void lp8x4x_eth1_mac_init(void)
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{
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u8 eth1addr[8];
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int i;
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u8 reg;
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eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
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if (!is_valid_ether_addr(eth1addr))
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return;
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for (i = 0, reg = 0x10; i < 6; i++, reg++) {
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writeb(reg, (u8 *)(DM9000_IO_2));
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writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
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}
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}
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int board_eth_init(bd_t *bis)
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{
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lp8x4x_eth1_mac_init();
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return dm9000_initialize(bis);
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}
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#endif
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