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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: Tom Rini <trini@ti.com>
189 lines
4.8 KiB
C
189 lines
4.8 KiB
C
/*
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* clock.c
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*
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* Clock initialization for AM33XX boards.
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* Derived from OMAP4 boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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static void setup_post_dividers(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, dpll_regs->cm_div_m3_dpll);
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if (params->m4 >= 0)
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writel(params->m4, dpll_regs->cm_div_m4_dpll);
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if (params->m5 >= 0)
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writel(params->m5, dpll_regs->cm_div_m5_dpll);
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if (params->m6 >= 0)
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writel(params->m6, dpll_regs->cm_div_m6_dpll);
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}
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static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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hang();
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}
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}
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static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("Bypassing DPLL failed 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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}
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}
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static void bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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do_bypass_dpll(dpll_regs);
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wait_for_bypass(dpll_regs);
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}
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void do_setup_dpll(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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u32 temp;
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if (!params)
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return;
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temp = readl(dpll_regs->cm_clksel_dpll);
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bypass_dpll(dpll_regs);
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/* Set M & N */
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, dpll_regs->cm_clksel_dpll);
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setup_post_dividers(dpll_regs, params);
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/* Wait till the DPLL locks */
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do_lock_dpll(dpll_regs);
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wait_for_lock(dpll_regs);
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}
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static void setup_dplls(void)
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{
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const struct dpll_params *params;
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params = get_dpll_core_params();
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do_setup_dpll(&dpll_core_regs, params);
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params = get_dpll_mpu_params();
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do_setup_dpll(&dpll_mpu_regs, params);
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params = get_dpll_per_params();
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do_setup_dpll(&dpll_per_regs, params);
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writel(0x300, &cmwkup->clkdcoldodpllper);
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params = get_dpll_ddr_params();
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do_setup_dpll(&dpll_ddr_regs, params);
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}
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static inline void wait_for_clk_enable(u32 *clkctrl_addr)
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{
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
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u32 bound = LDELAY;
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while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
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(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
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clkctrl = readl(clkctrl_addr);
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idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
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MODULE_CLKCTRL_IDLEST_SHIFT;
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if (--bound == 0) {
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printf("Clock enable failed for 0x%p idlest 0x%x\n",
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clkctrl_addr, clkctrl);
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return;
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}
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}
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}
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static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
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u32 wait_for_enable)
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{
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
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enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
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debug("Enable clock module - %p\n", clkctrl_addr);
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if (wait_for_enable)
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wait_for_clk_enable(clkctrl_addr);
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}
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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{
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
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enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
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debug("Enable clock domain - %p\n", clkctrl_reg);
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}
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void do_enable_clocks(u32 *const *clk_domains,
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u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
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{
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u32 i, max = 100;
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/* Put the clock domains in SW_WKUP mode */
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for (i = 0; (i < max) && clk_domains[i]; i++) {
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enable_clock_domain(clk_domains[i],
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
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}
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/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
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for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
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enable_clock_module(clk_modules_explicit_en[i],
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
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wait_for_enable);
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};
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}
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/*
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* Before scaling up the clocks we need to have the PMIC scale up the
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* voltages first. This will be dependent on which PMIC is in use
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* and in some cases we may not be scaling things up at all and thus not
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* need to do anything here.
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*/
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__weak void scale_vcores(void)
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{
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}
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void prcm_init()
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{
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enable_basic_clocks();
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scale_vcores();
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setup_dplls();
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}
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