mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 10:28:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
411 lines
13 KiB
C
411 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Sun6i platform dram controller init.
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/prcm.h>
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#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
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struct dram_sun6i_para {
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u8 bus_width;
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u8 chan;
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u8 rank;
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u8 rows;
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u16 page_size;
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};
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static void mctl_sys_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int dram_clk_div = 2;
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clock_set_pll5(DRAM_CLK * dram_clk_div, false);
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clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
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CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
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CCM_DRAMCLK_CFG_UPD);
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mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
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writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
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/* deassert mctl reset */
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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/* enable mctl clock */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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}
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static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_phy_reg *mctl_phy;
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if (ch_index == 0)
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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else
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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/* disable + reset dlls */
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
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}
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udelay(2);
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/* enable + reset dlls */
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writel(0, &mctl_phy->acdllcr);
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writel(0, &mctl_phy->dx0dllcr);
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writel(0, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(0, &mctl_phy->dx2dllcr);
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writel(0, &mctl_phy->dx3dllcr);
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}
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udelay(22);
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/* enable and release reset of dlls */
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writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
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}
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udelay(22);
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}
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static bool mctl_rank_detect(u32 *gsr0, int rank)
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{
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const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
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const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
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mctl_await_completion(gsr0, done, done);
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mctl_await_completion(gsr0 + 0x10, done, done);
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return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
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}
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static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg *mctl_ctl;
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struct sunxi_mctl_phy_reg *mctl_phy;
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if (ch_index == 0) {
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mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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} else {
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mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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}
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writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
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mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
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/* PHY initialization */
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writel(MCTL_PGCR, &mctl_phy->pgcr);
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writel(MCTL_MR0, &mctl_phy->mr0);
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writel(MCTL_MR1, &mctl_phy->mr1);
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writel(MCTL_MR2, &mctl_phy->mr2);
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writel(MCTL_MR3, &mctl_phy->mr3);
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writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
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&mctl_phy->ptr0);
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writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
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writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
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writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
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(MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
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(MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
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&mctl_phy->dtpr0);
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writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
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(MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
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((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
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(MCTL_TAOND << 0), &mctl_phy->dtpr1);
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writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
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(MCTL_TEXSR << 0), &mctl_phy->dtpr2);
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writel(1, &mctl_ctl->dfitphyupdtype0);
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writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
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writel(MCTL_DSGCR, &mctl_phy->dsgcr);
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writel(MCTL_DXCCR, &mctl_phy->dxccr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
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mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
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writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
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setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
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writel(MCTL_PIR_STEP1, &mctl_phy->pir);
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udelay(10);
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mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
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/* rank detect */
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if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
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para->rank = 1;
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clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
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}
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/*
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* channel detect, check channel 1 dx0 and dx1 have rank 0, if not
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* assume nothing is connected to channel 1.
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*/
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if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
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para->chan = 1;
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clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
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return;
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}
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/* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
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if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
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para->bus_width = 16;
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para->page_size = 2048;
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setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
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setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
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clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
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clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
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}
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setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
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writel(MCTL_PIR_STEP2, &mctl_phy->pir);
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udelay(10);
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mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
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if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
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panic("Training error initialising DRAM\n");
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/* Move to configure state */
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writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
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mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
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/* Set number of clks per micro-second */
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writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
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/* Set number of clks per 100 nano-seconds */
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writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
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/* Set memory timing registers */
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writel(MCTL_TREFI, &mctl_ctl->trefi);
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writel(MCTL_TMRD, &mctl_ctl->tmrd);
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writel(MCTL_TRFC, &mctl_ctl->trfc);
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writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
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writel(MCTL_TRTW, &mctl_ctl->trtw);
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writel(MCTL_TAL, &mctl_ctl->tal);
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writel(MCTL_TCL, &mctl_ctl->tcl);
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writel(MCTL_TCWL, &mctl_ctl->tcwl);
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writel(MCTL_TRAS, &mctl_ctl->tras);
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writel(MCTL_TRC, &mctl_ctl->trc);
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writel(MCTL_TRCD, &mctl_ctl->trcd);
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writel(MCTL_TRRD, &mctl_ctl->trrd);
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writel(MCTL_TRTP, &mctl_ctl->trtp);
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writel(MCTL_TWR, &mctl_ctl->twr);
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writel(MCTL_TWTR, &mctl_ctl->twtr);
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writel(MCTL_TEXSR, &mctl_ctl->texsr);
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writel(MCTL_TXP, &mctl_ctl->txp);
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writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
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writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
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writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
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writel(MCTL_TDQS, &mctl_ctl->tdqs);
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writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
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writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
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writel(MCTL_TCKE, &mctl_ctl->tcke);
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writel(MCTL_TMOD, &mctl_ctl->tmod);
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writel(MCTL_TRSTL, &mctl_ctl->trstl);
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writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
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writel(MCTL_TMRR, &mctl_ctl->tmrr);
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writel(MCTL_TCKESR, &mctl_ctl->tckesr);
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writel(MCTL_TDPD, &mctl_ctl->tdpd);
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/* Unknown magic performed by boot0 */
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setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
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clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
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/* Select 16/32-bits mode for MCTL */
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if (para->bus_width == 16)
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setbits_le32(&mctl_ctl->ppcfg, 1);
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/* Set DFI timing registers */
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writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
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writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
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writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
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writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
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writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
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/* DFI update configuration register */
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writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
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/* Move to access state */
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writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
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mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
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}
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static void mctl_com_init(struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy1 =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
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((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
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MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
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MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
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/* Unknown magic performed by boot0 */
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setbits_le32(&mctl_com->dbgcr, (1 << 6));
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if (para->chan == 1) {
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/* Shutdown channel 1 */
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setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
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setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
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clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
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/*
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* CH0 ?? this is what boot0 does. Leave as is until we can
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* confirm this.
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*/
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setbits_le32(&prcm->vdd_sys_pwroff,
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PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
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}
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}
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static void mctl_port_cfg(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* enable DRAM AXI clock for CPU access */
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setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
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/* Bunch of magic writes performed by boot0 */
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writel(0x00400302, &mctl_com->rmcr[0]);
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writel(0x01000307, &mctl_com->rmcr[1]);
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writel(0x00400302, &mctl_com->rmcr[2]);
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writel(0x01000307, &mctl_com->rmcr[3]);
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writel(0x01000307, &mctl_com->rmcr[4]);
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writel(0x01000303, &mctl_com->rmcr[6]);
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writel(0x01000303, &mctl_com->mmcr[0]);
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writel(0x00400310, &mctl_com->mmcr[1]);
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writel(0x01000307, &mctl_com->mmcr[2]);
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writel(0x01000303, &mctl_com->mmcr[3]);
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writel(0x01800303, &mctl_com->mmcr[4]);
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writel(0x01800303, &mctl_com->mmcr[5]);
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writel(0x01800303, &mctl_com->mmcr[6]);
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writel(0x01800303, &mctl_com->mmcr[7]);
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writel(0x01000303, &mctl_com->mmcr[8]);
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writel(0x00000002, &mctl_com->mmcr[15]);
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writel(0x00000310, &mctl_com->mbagcr[0]);
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writel(0x00400310, &mctl_com->mbagcr[1]);
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writel(0x00400310, &mctl_com->mbagcr[2]);
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writel(0x00000307, &mctl_com->mbagcr[3]);
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writel(0x00000317, &mctl_com->mbagcr[4]);
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writel(0x00000307, &mctl_com->mbagcr[5]);
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}
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unsigned long sunxi_dram_init(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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u32 offset;
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int bank, bus, columns;
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/* Set initial parameters, these get modified by the autodetect code */
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struct dram_sun6i_para para = {
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.bus_width = 32,
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.chan = 2,
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.rank = 2,
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.page_size = 4096,
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.rows = 16,
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};
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/* A31s only has one channel */
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if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
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para.chan = 1;
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mctl_sys_init();
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mctl_dll_init(0, ¶);
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setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
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if (para.chan == 2) {
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mctl_dll_init(1, ¶);
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setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
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}
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setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
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mctl_channel_init(0, ¶);
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if (para.chan == 2)
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mctl_channel_init(1, ¶);
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mctl_com_init(¶);
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mctl_port_cfg();
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/*
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* Change to 1 ch / sequence / 8192 byte pages / 16 rows /
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* 8 bit banks / 1 rank mode.
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*/
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clrsetbits_le32(&mctl_com->cr,
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MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
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MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
|
|
MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
|
|
MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
|
|
MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
|
|
|
|
/* Detect and set page size */
|
|
for (columns = 7; columns < 20; columns++) {
|
|
if (mctl_mem_matches(1 << columns))
|
|
break;
|
|
}
|
|
bus = (para.bus_width == 32) ? 2 : 1;
|
|
columns -= bus;
|
|
para.page_size = (1 << columns) * (bus << 1);
|
|
clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
|
|
MCTL_CR_PAGE_SIZE(para.page_size));
|
|
|
|
/* Detect and set rows */
|
|
for (para.rows = 11; para.rows < 16; para.rows++) {
|
|
offset = 1 << (para.rows + columns + bus);
|
|
if (mctl_mem_matches(offset))
|
|
break;
|
|
}
|
|
clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
|
|
MCTL_CR_ROW(para.rows));
|
|
|
|
/* Detect bank size */
|
|
offset = 1 << (para.rows + columns + bus + 2);
|
|
bank = mctl_mem_matches(offset) ? 0 : 1;
|
|
|
|
/* Restore interleave, chan and rank values, set bank size */
|
|
clrsetbits_le32(&mctl_com->cr,
|
|
MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
|
|
MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
|
|
MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
|
|
MCTL_CR_RANK(para.rank));
|
|
|
|
return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
|
|
}
|