mirror of
https://github.com/brain-hackers/u-boot-brain
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![Eugen Hristev](/assets/img/avatar_default.png)
Enable the green led on SPL completion. Red led has no pulldown and it will be lighted by default when the board starts up. If the PMIC is not configured to enable LDO2, the leds will not light. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
230 lines
5.8 KiB
C
230 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Microchip Technology, Inc.
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* Eugen Hristev <eugen.hristev@microchip.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5d2.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_late_init(void)
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{
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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static void board_uart0_hw_init(void)
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{
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
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at91_periph_clk_enable(ATMEL_ID_UART0);
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}
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void board_debug_uart_init(void)
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{
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board_uart0_hw_init();
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#define MAC24AA_MAC_OFFSET 0xfa
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int misc_init_r(void)
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{
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#ifdef CONFIG_I2C_EEPROM
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at91_set_ethaddr(MAC24AA_MAC_OFFSET);
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#endif
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return 0;
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}
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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/* must set PB25 low to enable the CAN transceivers */
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static void board_can_stdby_dis(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
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}
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static void board_leds_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
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}
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/* deassert reset lines for external periph in case of warm reboot */
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static void board_reset_additional_periph(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
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}
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static void board_start_additional_periph(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
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}
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#ifdef CONFIG_SD_BOOT
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void spl_mmc_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
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at91_periph_clk_enable(ATMEL_ID_SDMMC0);
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}
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#endif
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void spl_board_init(void)
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{
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#ifdef CONFIG_SD_BOOT
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spl_mmc_init();
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#endif
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board_reset_additional_periph();
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board_can_stdby_dis();
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board_leds_init();
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}
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void spl_display_print(void)
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{
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}
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void spl_board_prepare_for_boot(void)
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{
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board_start_additional_periph();
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
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ATMEL_MPDDRC_CR_DIC_DS |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddrc->rtr = 0x298;
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ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
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(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
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ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
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(29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
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(10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
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ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
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(7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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struct atmel_mpddrc_config ddrc_config;
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u32 reg;
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ddrc_conf(&ddrc_config);
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(AT91_PMC_DDR, &pmc->scer);
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reg = readl(&mpddrc->io_calibr);
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
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reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
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reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
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writel(reg, &mpddrc->io_calibr);
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writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
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&mpddrc->rd_data_path);
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ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
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writel(0x5355, &mpddrc->cal_mr4);
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writel(64, &mpddrc->tim_cal);
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}
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void at91_pmc_init(void)
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{
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u32 tmp;
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/*
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* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
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* so we need to slow down and configure MCKR accordingly.
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* This is why we have a special flavor of the switching function.
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*/
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tmp = AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_MAIN;
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at91_mck_init_down(tmp);
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(82) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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tmp = AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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