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https://github.com/brain-hackers/u-boot-brain
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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
139 lines
2.8 KiB
C
139 lines
2.8 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined (CONFIG_IMX)
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#include <asm/arch/imx-regs.h>
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int timer_init (void)
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{
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int i;
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/* setup GP Timer 1 */
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TCTL1 = TCTL_SWR;
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for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
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TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
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TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
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reset_timer_masked();
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return (0);
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}
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/*
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* timer without interrupts
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*/
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base)
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{
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return get_timer_masked() - base;
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}
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void set_timer (ulong t)
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{
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/* nop */
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}
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void reset_timer_masked (void)
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{
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TCTL1 &= ~TCTL_TEN;
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TCTL1 |= TCTL_TEN; /* Enable timer */
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}
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ulong get_timer_masked (void)
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{
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return TCN1;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong endtime = get_timer_masked() + usec;
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signed long diff;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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void __udelay (unsigned long usec)
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{
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udelay_masked(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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{
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ulong tbclk;
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tbclk = CONFIG_SYS_HZ;
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return tbclk;
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}
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/*
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* Reset the cpu by setting up the watchdog timer and let him time out
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*/
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void reset_cpu (ulong ignored)
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{
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/* Disable watchdog and set Time-Out field to 0 */
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WCR = 0x00000000;
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/* Write Service Sequence */
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WSR = 0x00005555;
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WSR = 0x0000AAAA;
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/* Enable watchdog */
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WCR = 0x00000001;
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while (1);
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/*NOTREACHED*/
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}
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#endif /* defined (CONFIG_IMX) */
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