mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-20 03:33:20 +09:00
1b4f25ff8e
When not relying on Coreboot for GPIO init the GPIOs must be set up correctly. This is currently done statically through a rather ugly method. As the GPIOs are figured out they can be moved to the device tree and set up as needed rather than all at the start. In this implementation, board files should call ich_gpio_set_gpio_map() before the GPIO driver is used in order to provide the GPIO information. We use the early PCI interface so that this driver can now be used before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
244 lines
7.0 KiB
C
244 lines
7.0 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot src/southbridge/intel/bd82x6x/pch.h
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_PCH_H
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#define _ASM_ARCH_PCH_H
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#include <pci.h>
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#define DEFAULT_GPIOBASE 0x0480
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#define DEFAULT_PMBASE 0x0500
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#define SMBUS_IO_BASE 0x0400
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#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
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#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
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#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
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#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
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#define PCH_PCIE_DEV_SLOT 28
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#define PCH_DEV PCI_BDF(0, 0, 0)
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#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0xDC
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_ROUT 0xb8
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
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#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
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#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
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/* PCI Configuration Space (D31:F3): SMBus */
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#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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#define SMB_RCV_SLVA 0x09
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* SMBus I/O bits. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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/* Root Complex Register Block */
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#define DEFAULT_RCBA 0xfed1c000
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#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
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#define PCH_RCBA_BASE 0xf0
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#define VCH 0x0000 /* 32bit */
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#define VCAP1 0x0004 /* 32bit */
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#define VCAP2 0x0008 /* 32bit */
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#define PVC 0x000c /* 16bit */
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#define PVS 0x000e /* 16bit */
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#define V0CAP 0x0010 /* 32bit */
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#define V0CTL 0x0014 /* 32bit */
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#define V0STS 0x001a /* 16bit */
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#define V1CAP 0x001c /* 32bit */
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#define V1CTL 0x0020 /* 32bit */
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#define V1STS 0x0026 /* 16bit */
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#define RCTCL 0x0100 /* 32bit */
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#define ESD 0x0104 /* 32bit */
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#define ULD 0x0110 /* 32bit */
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#define ULBA 0x0118 /* 64bit */
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#define RP1D 0x0120 /* 32bit */
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#define RP1BA 0x0128 /* 64bit */
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#define RP2D 0x0130 /* 32bit */
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#define RP2BA 0x0138 /* 64bit */
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#define RP3D 0x0140 /* 32bit */
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#define RP3BA 0x0148 /* 64bit */
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#define RP4D 0x0150 /* 32bit */
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#define RP4BA 0x0158 /* 64bit */
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#define HDD 0x0160 /* 32bit */
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#define HDBA 0x0168 /* 64bit */
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#define RP5D 0x0170 /* 32bit */
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#define RP5BA 0x0178 /* 64bit */
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#define RP6D 0x0180 /* 32bit */
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#define RP6BA 0x0188 /* 64bit */
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#define RPC 0x0400 /* 32bit */
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#define RPFN 0x0404 /* 32bit */
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#define SPI_FREQ_SWSEQ 0x3893
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#define SPI_DESC_COMP0 0x38b0
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#define SPI_FREQ_WR_ERA 0x38b4
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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#define RC 0x3400 /* 32bit */
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#define HPTC 0x3404 /* 32bit */
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#define GCS 0x3410 /* 32bit */
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#define BUC 0x3414 /* 32bit */
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#define PCH_DISABLE_GBE (1 << 5)
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#define FD 0x3418 /* 32bit */
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#define DISPBDF 0x3424 /* 16bit */
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#define FD2 0x3428 /* 32bit */
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#define CG 0x341c /* 32bit */
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GPIO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define GPIO_USE_SEL3 0x40
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#define GP_IO_SEL3 0x44
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#define GP_LVL3 0x48
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#define GP_RST_SEL1 0x60
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#define GP_RST_SEL2 0x64
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#define GP_RST_SEL3 0x68
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define PROC_CNT 0x10
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#define LV2 0x14
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#define LV3 0x15
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#define LV4 0x16
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#define PM2_CNT 0x50 /* mobile only */
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#define GPE0_STS 0x20
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#define PME_B0_STS (1 << 13)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define RI_STS (1 << 8)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN 0x28
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define TCOSCI_EN (1 << 6)
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#define SMI_EN 0x30
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#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
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#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
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#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
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#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
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#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
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#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
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#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
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#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
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#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
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#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
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#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
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#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
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#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GPE_CNTL 0x42
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#define DEVACT_STS 0x44
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#define SS_CNT 0x50
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#define C3_RES 0x54
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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/**
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* lpc_early_init() - set up LPC serial ports and other early things
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*
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* @blob: Device tree blob
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* @node: Offset of LPC node
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* @dev: PCH PCI device containing the LPC
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* @return 0 if OK, -ve on error
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*/
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int lpc_early_init(const void *blob, int node, pci_dev_t dev);
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#endif
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