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https://github.com/brain-hackers/u-boot-brain
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![Trent Piepho](/assets/img/avatar_default.png)
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
308 lines
7.1 KiB
C
308 lines
7.1 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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int
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checkcpu(void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint ver;
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uint major, minor;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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puts("Freescale PowerPC\n");
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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puts("CPU:\n");
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puts(" Core: ");
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switch (ver) {
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case PVR_VER(PVR_86xx):
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{
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uint msscr0 = mfspr(MSSCR0);
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printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
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if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
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puts("\n Core1Translation Enabled");
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debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
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}
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts(" System: ");
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switch (ver) {
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case SVR_8641:
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if (SVR_SUBVER(svr) == 1) {
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puts("8641D");
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} else {
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puts("8641");
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}
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break;
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case SVR_8610:
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puts("8610");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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get_sys_info(&sysinfo);
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puts(" Clocks: ");
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printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
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printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
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printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02x)\n",
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sysinfo.freqLocalBus);
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}
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puts(" L2: ");
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if (get_l2cr() & 0x80000000)
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puts("Enabled\n");
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else
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puts("Disabled\n");
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return 0;
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}
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static inline void
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soft_restart(unsigned long addr)
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{
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#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
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/*
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* SRR0 has system reset vector, SRR1 has default MSR value
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* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
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*/
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__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
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__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
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__asm__ __volatile__ ("mtspr 27, 4");
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__asm__ __volatile__ ("rfi");
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#else /* CONFIG_MPC8641HPCN */
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out8(PIXIS_BASE + PIXIS_RST, 0);
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#endif /* !CONFIG_MPC8641HPCN */
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while (1) ; /* not reached */
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}
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/*
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* No generic way to do board reset. Simply call soft_reset.
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*/
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void
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do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
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#ifdef CONFIG_SYS_RESET_ADDRESS
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ulong addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
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* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
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* address. Better pick an address known to be invalid on your
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* system and assign it to CONFIG_SYS_RESET_ADDRESS.
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*/
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ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
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#endif
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/* flush and disable I/D cache */
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__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
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__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
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__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
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__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 4");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 5");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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soft_restart(addr);
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#else /* CONFIG_MPC8641HPCN */
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out8(PIXIS_BASE + PIXIS_RST, 0);
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#endif /* !CONFIG_MPC8641HPCN */
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while (1) ; /* not reached */
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long
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get_tbclk(void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return (sys_info.freqSystemBus + 3L) / 4L;
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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#if defined(CONFIG_MPC8610)
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/*
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* This actually feed the hard enabled watchdog.
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*/
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_wdt_t *wdt = &immap->im_wdt;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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u32 tmp = gur->pordevsr;
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if (tmp & 0x4000) {
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wdt->swsrr = 0x556c;
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wdt->swsrr = 0xaa39;
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}
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#endif
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void
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dma_init(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->satr0 = 0x00040000;
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dma->datr0 = 0x00040000;
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asm("sync; isync");
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}
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uint
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dma_check(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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volatile uint status = dma->sr0;
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/* While the channel is busy, spin */
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while ((status & 4) == 4) {
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status = dma->sr0;
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}
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if (status != 0) {
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printf("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int
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dma_xfer(void *dest, uint count, void *src)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->dar0 = (uint) dest;
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dma->sar0 = (uint) src;
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dma->bcr0 = count;
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dma->mr0 = 0xf000004;
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asm("sync;isync");
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dma->mr0 = 0xf000005;
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asm("sync;isync");
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return dma_check();
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}
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#endif /* CONFIG_DDR_ECC */
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0, and BATs
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*/
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void mpc86xx_reginfo(void)
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{
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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ccsr_lbc_t *lbc = &immap->im_lbc;
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print_bats();
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print_laws();
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printf ("Local Bus Controller Registers\n"
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"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
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printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
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printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
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printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
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printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
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printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
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printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
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printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_TSEC_ENET)
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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